/*******************************************************************************
 *
 * MODULE dramtests.h
 *
 * DESCRIPTION Header file for cmd_dramtests.c
 *
 * THIS PROGRAM AND THE INFORMATION CONTAINED HEREIN IS THE PROPERTY OF
 * ATTO TECHNOLOGY, INC. AND SHALL NOT BE REPORDUCED, COPIED, OR USED IN
 * WHOLE OR IN PART OTHER THAN AS PROVIDED FOR IN THE LICENSE AGREEMENT
 * PURSUANT TO WHICH IT WAS FURNISHED.
 *
 * COPYRIGHT (c) ATTO TECHNOLOGY, INC, 2016
 * ALL RIGHTS RESERVED
 *
 ******************************************************************************/

#ifndef __DRAMTESTS_H__
#define __DRAMTESTS_H__

#define ATTO_KERNEL_ADDR_A        	0x01AA0000
#define ATTO_DEVICE_TREE_ADDR_A   	0x01A80000
#define ATTO_KERNEL_ADDR_A_STR     	__stringify(ATTO_KERNEL_ADDR_A)
#define ATTO_DEVICE_TREE_ADDR_A_STR	__stringify(ATTO_DEVICE_TREE_ADDR_A)
#define ATTO_IMAGE_A_ROOT			"/dev/mtdblock10"

#define ATTO_KERNEL_ADDR_B      	0x056C0000
#define ATTO_DEVICE_TREE_ADDR_B 	0x056A0000
#define ATTO_KERNEL_ADDR_B_STR     	__stringify(ATTO_KERNEL_ADDR_B)
#define ATTO_DEVICE_TREE_ADDR_B_STR	__stringify(ATTO_DEVICE_TREE_ADDR_B)
#define ATTO_IMAGE_B_ROOT			"/dev/mtdblock15"

#define ARRIA10_HPS_RST_MGR_RST_REG 0xFFD0500C
	#define ARRIA10_RST_WARM			0x00000002

#define ARRIA10_HPS_OSC1_TIMER1_BASE	0xffd00100
	#define TIMER_CURRENTVAL_OFFSET	0x00000004
	#define TEN_MS_MAGIC_NUM		0x0003d090

/* TEST ENGINE REGISTER DEFINES */
#define BAU_DDR_TE_CTRL_OFFSET			0x00000000
	/* offsets into ctrl/status register */
	#define BAU_DDR_TE_CTRL_RUN_MASK	0x0001
	#define BAU_DDR_TE_CTRL_TEST_MASK	0x0002
	#define BAU_DDR_TE_STS_FAIL			0x1000
	/* run types */
	#define BAU_DDR_TE_RANDOMRUN	0x0004
	#define BAU_DDR_TE_READONLY		0x0008
	#define BAU_DDR_TE_MISALIGNXFER	0x0010
	#define BAU_DDR_TE_DELAY		0x0020
	#define BAU_DDR_TE_CONTRUN		0x0040
	#define BAU_DDR_TE_STOPONFAIL	0x0080
	/* pattern types */
	#define BAU_DDR_TE_TP_MASK			0x0f00
	#define BAU_DDR_TE_TP_RANDOM		0x0000 /* 0 */
	#define BAU_DDR_TE_TP_INVERTING		0x0100 /* 1 */
	#define BAU_DDR_TE_TP_NONINVERTING	0x0200 /* 2 */
	#define BAU_DDR_TE_TP_WALKINGBIT	0x0300 /* 3 */
	#define BAU_DDR_TE_TP_WALKINGNIBBLE	0x0400 /* 4 */
	#define BAU_DDR_TE_TP_ADDRESS		0x0500 /* 5 */
	#define BAU_DDR_TE_TP_MARCHUP		0x0600 /* 6 */
	#define BAU_DDR_TE_TP_MARCHDOWN		0x0700 /* 7 */
	/* The marchc test has many patterns. 16 should not actually be written to 
	 * the pattern register because it will overflow the 4 bits available 
	 */
	#define BAU_DDR_TE_TP_MARCHC		0x1000 /* 16 */
#define BAU_DDR_TE_XFERSIZE_OFFSET		0x00000002
#define BAU_DDR_TE_STARTADDR_OFFSET		0x00000008
#define BAU_DDR_TE_MAGIC_OFFSET			0x00000010
	#define BAU_DDR_TE_MAGIC_NUMBER		0x12345678
#define BAU_DDR_TE_NUMBYTES_OFFSET		0x0000000c
#define BAU_DDR_TE_SEED0_OFFSET			0x00000010
#define BAU_DDR_TE_SEED1_OFFSET			0x00000014
#define BAU_DDR_TE_SEED2_OFFSET			0x00000018
#define BAU_DDR_TE_SEED3_OFFSET			0x0000001c
#define BAU_DDR_TE_ERRORADDR_OFFSET		0x00000020
	#define BAU_DDR_TE_NUMBYTELANES	16
	#define BCE_DDR_TE_NUMBYTELANES	4
#define BAU_DDR_TE_ERRORDWORD0_OFFSET	0x00000040
#define BAU_DDR_TE_ERRORDWORD1_OFFSET	0x00000044
#define BAU_DDR_TE_ERRORDWORD2_OFFSET	0x00000048
#define BAU_DDR_TE_ERRORDWORD3_OFFSET	0x0000004c
#define BAU_DDR_TE_ERRORDWORD4_OFFSET	0x00000050
#define BAU_DDR_TE_ERRORDWORD5_OFFSET	0x00000041
#define BAU_DDR_TE_ERRORDWORD6_OFFSET	0x00000048
#define BAU_DDR_TE_ERRORDWORD7_OFFSET	0x0000005c
#define BAU_DDR_TE_ERRORDWORD8_OFFSET	0x00000060
#define BAU_DDR_TE_ERRORDWORD9_OFFSET	0x00000064
#define BAU_DDR_TE_ERRORDWORD10_OFFSET	0x00000068
#define BAU_DDR_TE_ERRORDWORD11_OFFSET	0x0000006c
#define BAU_DDR_TE_ERRORDWORD12_OFFSET	0x00000070
#define BAU_DDR_TE_ERRORDWORD13_OFFSET	0x00000074
#define BAU_DDR_TE_ERRORDWORD14_OFFSET	0x00000078
#define BAU_DDR_TE_ERRORDWORD15_OFFSET	0x0000007c

#define BAU_DDR4_TE_0_BASE		0xc8081000
#define BAU_DDR4_TE_1_BASE		0xc8081800
#define BCE_DDR4_TE_BASE		0xc0084000
#define BCE_DDR4_TE_BASE_OLD	0xc0084000

/* ECC Regs */
#define BAU_ECC_CFG_OFFSET			0x00000200
	#define BAU_DDR_CFG_ECCENABLE_MASK    0x00000001
#define BAU_ECC_CTRL_OFFSET			0x00000208
	#define BAU_ECC_CTRL_SBE_ENABLE	0x00000001
	#define BAU_ECC_CTRL_DBE_ENABLE	0x00000002
	#define BAU_ECC_CTRL_ENABLE		(BAU_ECC_CTRL_SBE_ENABLE \
			                       | BAU_ECC_CTRL_DBE_ENABLE)
	#define BAU_ECC_CTRL_INT_ENABLE	0x00000004
	#define BAU_ECC_CTRL_CLEAR		0x00000080
#define BAU_ECC_STATUS_OFFSET		0x00000240
	#define BAU_ECC_STATUS_SBE	0x00000002
	#define BAU_ECC_STATUS_DBE	0x00000004
	#define BAU_ECC_STATUS_DRP	0x00000008
#define BAU_ECC_ERROR_ADDR_OFFSET	0x00000244

#define BCE_ECC_BASE            0xffcfb000
#define BCE_ECC_ECCCNTRL_1_REG  (BCE_ECC_BASE + 0x100)
	#define BCE_ECC_ECCCNTRL_1_ECC_EN_MASK    0x00000001
#define BCE_ECC_INTEN_REG	    (BCE_ECC_BASE + 0x110)
	#define BCE_ECC_INTEN_MASK	0x00000007
#define BCE_ECC_STATUS_REG	    (BCE_ECC_BASE + 0x120)
	#define BCE_ECC_SBE_MASK	0x00000001
	#define BCE_ECC_DBE_MASK	0x00000002
	#define BCE_ECC_CLEAR_MASK	0x00070007
#define BCE_ECC_DBE_ERRADDR_REG	(BCE_ECC_BASE + 0x12c)
#define BCE_ECC_SBE_ERRADDR_REG	(BCE_ECC_BASE + 0x130)

#define BAU_DDR_0_CTRL_BASE			0xc8180000
#define BAU_DDR_0_CFG_REG			(BAU_DDR_0_CTRL_BASE + BAU_ECC_CFG_OFFSET)
#define BAU_DDR_0_CTRL_REG			(BAU_DDR_0_CTRL_BASE + BAU_ECC_CTRL_OFFSET)
#define BAU_DDR_0_STATUS_REG		(BAU_DDR_0_CTRL_BASE \
		                           + BAU_ECC_STATUS_OFFSET)
#define BAU_DDR_0_ERROR_ADDR_REG	(BAU_DDR_0_CTRL_BASE \
		                           + BAU_ECC_ERROR_ADDR_OFFSET)

#define BAU_DDR_1_CTRL_BASE			0xc81c0000
#define BAU_DDR_1_CFG_REG			(BAU_DDR_1_CTRL_BASE + BAU_ECC_CFG_OFFSET)
#define BAU_DDR_1_CTRL_REG			(BAU_DDR_1_CTRL_BASE + BAU_ECC_CTRL_OFFSET)
#define BAU_DDR_1_STATUS_REG		(BAU_DDR_1_CTRL_BASE \
		                           + BAU_ECC_STATUS_OFFSET)
#define BAU_DDR_1_ERROR_ADDR_REG	(BAU_DDR_1_CTRL_BASE \
		                           + BAU_ECC_ERROR_ADDR_OFFSET)

/* volatile typedefs */
typedef volatile uint32_t vuint32_t;
typedef volatile uint16_t vuint16_t;
typedef volatile uint8_t vuint8_t;

typedef struct bau_dram_test
{
	uint32_t base_addr;
	uint32_t size;
	uint16_t pattern;
	uint16_t time_to_run; /* not implemented */
	uint32_t seed0;
	uint32_t seed1;
	uint32_t seed2;
	uint32_t seed3;
} BAU_DRAM_TEST, *PBAU_DRAM_TEST;

#define BAU_DRAM_SIZE           0x80000000
#define BCE_DRAM_SIZE           0x40000000
#define BAU_DRAM_MIN_TEST_SIZE	0x00000400
#define BAU_DRAM_TEST_SIZE      0x80000000
/* Uboot uses upper 2MB of BCE memory so upper 2MB can't be tested */
#define BCE_DRAM_TEST_SIZE      0x3FE00000  
#define RUN_NORMAL_POST         0
#define RUN_EXTENDED_POST       1

#define MC_STATE_NONE				0
#define MC_STATE_MARCHUP			1
#define MC_STATE_MARCHUP_INV		2
#define MC_STATE_VERIFY_MARCHUP		3
#define MC_STATE_MARCHDOWN			4
#define MC_STATE_MARCHDOWN_INV		5
#define MC_STATE_VERIFY_MARCHDOWN	6

#define BAU_DRAM_TEST_RANDOM \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_RANDOM, \
		.time_to_run = 0, \
		.seed0 = 0x12345678, \
		.seed1 = 0x33452199, \
		.seed2 = 0xfacef00d, \
		.seed3 = 0xdeadf00d \
}

#define BAU_DRAM_TEST_NONINVERTING \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_NONINVERTING, \
		.time_to_run = 5, \
		.seed0 = 0x00000000, \
		.seed1 = 0x00000000, \
		.seed2 = 0x00000000, \
		.seed3 = 0x00000000 \
}

#define BAU_DRAM_TEST_A5_NONINVERTING \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_NONINVERTING, \
		.time_to_run = 5, \
		.seed0 = 0xA5A5A5A5, \
		.seed1 = 0xA5A5A5A5, \
		.seed2 = 0xA5A5A5A5, \
		.seed3 = 0xA5A5A5A5 \
}

#define BAU_DRAM_TEST_5A_NONINVERTING \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_NONINVERTING, \
		.time_to_run = 5, \
		.seed0 = 0x5A5A5A5A, \
		.seed1 = 0x5A5A5A5A, \
		.seed2 = 0x5A5A5A5A, \
		.seed3 = 0x5A5A5A5A \
}

#define BAU_DRAM_TEST_MARCHC1 \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_MARCHC, \
		.time_to_run = 5, \
		.seed0 = 0x00000000, \
		.seed1 = 0x00000000, \
		.seed2 = 0x00000000, \
		.seed3 = 0x00000000 \
}

#define BAU_DRAM_TEST_MARCHC2 \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_MARCHC, \
		.time_to_run = 5, \
		.seed0 = 0x55555555, \
		.seed1 = 0x55555555, \
		.seed2 = 0x55555555, \
		.seed3 = 0x55555555 \
}

#define BAU_DRAM_TEST_MARCHC3 \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_MARCHC, \
		.time_to_run = 5, \
		.seed0 = 0x33333333, \
		.seed1 = 0x33333333, \
		.seed2 = 0x33333333, \
		.seed3 = 0x33333333 \
}

#define BAU_DRAM_TEST_MARCHC4 \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_MARCHC, \
		.time_to_run = 5, \
		.seed0 = 0x0f0f0f0f, \
		.seed1 = 0x0f0f0f0f, \
		.seed2 = 0x0f0f0f0f, \
		.seed3 = 0x0f0f0f0f \
}

#define BAU_DRAM_TEST_MARCHC5 \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_MARCHC, \
		.time_to_run = 5, \
		.seed0 = 0x00ff00ff, \
		.seed1 = 0x00ff00ff, \
		.seed2 = 0x00ff00ff, \
		.seed3 = 0x00ff00ff \
}

#define BAU_DRAM_TEST_MARCHC6 \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_MARCHC, \
		.time_to_run = 5, \
		.seed0 = 0x0000ffff, \
		.seed1 = 0x0000ffff, \
		.seed2 = 0x0000ffff, \
		.seed3 = 0x0000ffff \
}

#define BAU_DRAM_TEST_MARCHC7 \
{ \
		.base_addr = 0, \
		.size = BAU_DRAM_MIN_TEST_SIZE, \
		.pattern = BAU_DDR_TE_TP_MARCHC, \
		.time_to_run = 5, \
		.seed0 = 0xffffffff, \
		.seed1 = 0x00000000, \
		.seed2 = 0xffffffff, \
		.seed3 = 0x00000000 \
}

/* use the size param to determine if this is the struct you're looking at */
#define BAU_DRAM_TEST_NULL \
{ \
		.base_addr = 0, \
		.size = 0, \
		.pattern = 0, \
		.time_to_run = 0, \
		.seed0 = 0, \
		.seed1 = 0, \
		.seed2 = 0, \
		.seed3 = 0 \
}

uint32_t read_timer_current_val(void)
{
	volatile uint32_t * p = 
			(volatile uint32_t *)ARRIA10_HPS_OSC1_TIMER1_BASE 
			                   + TIMER_CURRENTVAL_OFFSET;
	return *p;
}

#endif /* __DRAMTESTS_H__ */