/*-------------------------------------------------------------------------------------------------------------------*/ /* ----------------------------------------------AST2500EVB Configuration -------------------------------------------*/ /*-------------------------------------------------------------------------------------------------------------------*/ #ifndef __AST2500EVB_H__ #define __AST2500EVB_H__ #include #include #include /* File Systems to be suported */ #define CONFIG_FS_FAT 1 #define CONFIG_CMD_FAT 1 #define CONFIG_CMD_EXT2 1 #define CONFIG_CMD_EXT4 1 #define CONFIG_FS_EXT2 1 #define CONFIG_FS_EXT4 1 #define CONFIG_FS_GENERIC 1 /* Overerride defaults */ #undef DEBUG #undef CONFIG_SYS_ALT_MEMTEST /* This arm1176 core. Undefine other cores */ #undef CONFIG_ARM926EJS #define CONFIG_ARM1176 1 //Quanta++ #define ASTMMC_DDR4_MANUAL_RPD 0x8 #define ASTMMC_DDR4_MANUAL_RPU 0x5 //#define CONFIG_BOOTFILE rom.ima #define CONFIG_BOARDID FF #define CONFIG_FWU_ALL tftp 82000000; protect off all; erase all; cp.b 82000000 20000000 2000000 #define CONFIG_FWU_BOOT tftp 82000000; protect off all; erase 14000000 1403ffff; cp.b 82000000 20000000 40000 #define CONFIG_FWU_OS tftp 82000000; protect off all; erase 14140000 1533ffff; cp.b 82140000 20140000 1200000 /*--------------------------------------------------------------- * EEPROM (AT24C128/AT24C64) configuration *--------------------------------------------------------------- */ #define CONFIG_CMD_EEPROM 1 /* EEPROM Support */ #ifdef CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_BUS CONFIG_SPX_FEATURE_GLOBAL_UBOOT_ENABLE_I2C_BUS #define CONFIG_I2C_CHANNEL_ID CONFIG_SPX_FEATURE_GLOBAL_UBOOT_ENABLE_I2C_BUS #define CONFIG_SYS_EEPROM_ADDR 0x54 //quanta+ slave address(7 bits) 0x54 = 0xA8 >> 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 //#define CONFIG_EEPROM_PAGE_WRITE_BITS 6 /* 64-byte pages */ //#define CONFIG_EEPROM_PAGE_WRITE_ENABLE //#define CONFIG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 mS */ #endif /*--------------------------------------------------------------- * Network Configuration *--------------------------------------------------------------*/ #define CONFIG_MACADDR_IN_EEPROM 1 #define CONFIG_EEPROM_MACADDR_OFFSET 6160 /* GUID_EEPROM_OFFSET (6k+16) */ #define CONFIG_EEPROM_MAC1ADDR_OFFSET 6166 /* CFG_EEPROM_MACADDR_OFFSET + 6 */ /*---------------------------------------------------------- * Board ID *---------------------------------------------------------- */ #define CONFIG_BOARDID_IN_EEPROM 1 #define CFG_EEPROM_FRU_OFFSET 0 //++Quanta /* Fixed values for board */ #define CONFIG_BOARD_NAME "AST2500EVB" #define CONFIG_CONS_INDEX 5 #define CONFIG_AST2500 1 #define CONFIG_AST2500EVB 1 #define CONFIG_BOARD_EARLY_INIT_F 1 /* BigPhys Area*/ #ifdef CONFIG_SPX_FEATURE_GLOBAL_FRAME_BUFFER_SUPPORT #define CONFIG_BIGPHYSAREA "8192" #define CONFIG_BOOTLOGO_SUPPORT 1 //Show Logo during Booting #define CONFIG_DISPLAY_ADDRESS 0x83000000 #else // Quanta, Integrate ASPEED provided JPEG capture engine for VNC usage, and required additional 16MB for JPEG engine use. #define CONFIG_BIGPHYSAREA "10240" // "6144" #endif /* Overerride Dram locations*/ #undef CONFIG_SYS_SDRAM_BASE #undef CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) /* Yafu Image downloading locations */ #define YAFU_IMAGE_UPLOAD_LOCATION (CONFIG_SYS_SDRAM_BASE + 0x02000000) #define YAFU_TEMP_SECTOR_BUFFER (CONFIG_SYS_SDRAM_BASE + 0x04000000) /* Defaut Memory Test Range */ #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x01000000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x05000000) /* Flash Operation Mode Mask */ #define CONFIG_FLASH_OPERATION_MODE_MASK 0x0001000F /* I2C EEPROM (AT24C128) configuration */ //#define CONFIG_I2C_CHANNEL_ID CONFIG_SPX_FEATURE_GLOBAL_UBOOT_ENABLE_I2C_BUS //#define CONFIG_SYS_EEPROM_ADDR 0x50 //#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Network Configuration */ //#undef CONFIG_MACADDR_IN_EEPROM //#define CONFIG_CMD_EEPROM 0 //#define CONFIG_EEPROM_MACADDR_OFFSET 0x00 //#define CONFIG_EEPROM_MAC1ADDR_OFFSET 0x08 /*-------------------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------- * QUANTA_OEM_INIT *---------------------------------------------------------- */ /* * This macro will be called by board_init() * We can config multi-function pin and GPIO pin here. * */ #define QUANTA_OEM_INIT \ do { \ unsigned long reg32; \ \ /* SCU00 Protection Key Register */ \ *((volatile u_long *) 0x1e6e2000) = 0x1688a8a8; /* Unlock SCU register*/ \ \ /* SCU7C Silicon Revision ID Register */ \ *((volatile u_long *) 0x1e6e207C) = 0x00647048;/**/ \ /* SCU04 System Reset Control Register */ \ reg32 = *((volatile u_long *) 0x1e6e2004); \ reg32 = reg32 & ~(1<<9); /* Reset PWM controller no operation */ \ *((volatile u_long *) 0x1e6e2004) = reg32; \ \ /* SCU70 Config Hardware Trapping reg */ \ reg32 = *((volatile u_long *) 0x1e6e2070); \ reg32 = reg32 | (1<<22); /* Enable GPIOE pass-through mode*/ \ *((volatile u_long *) 0x1e6e2070) = reg32; \ \ /* SCUA8 Multi-function Pin Control #9 */ \ reg32 = *((volatile u_long *) 0x1e6e20A8); \ reg32 = reg32 | (1<<26); /* Enable debounced GPIOE4 to GPIOE5 */ \ reg32 = reg32 | (1<<25); /* Enable debounced GPIOE2 to GPIOE3 */ \ reg32 = reg32 | (1<<24); /* Enable debounced GPIOE0 to GPIOE1 */ \ *((volatile u_long *) 0x1e6e20A8) = reg32; \ \ /* SCU84 Multi-function Pin Control #2 = 0x0000F000 => 0xFFFFFB00 */ \ reg32 = *((volatile u_long *) 0x1e6e2084); \ /*reg32 = reg32 | (1<<31); Enable UART2 RXD1 or VPB9 */ \ /*reg32 = reg32 | (1<<30); Enable UART2 TXD1 or VPB8 */ \ /*reg32 = reg32 | (1<<29); Enable UART2 NRTS1 or VPB7 */ \ /*reg32 = reg32 | (1<<28); Enable UART2 NDTR1 or VPB6 */ \ /*reg32 = reg32 | (1<<27); Enable UART2 NRI1 or VPB5 */ \ /*reg32 = reg32 | (1<<26); Enable UART2 NDSR1 or VPB4 */ \ /*reg32 = reg32 | (1<<25); Enable UART2 NDCD1 or VPB3 */ \ /*reg32 = reg32 | (1<<24); Enable UART2 NCTS1 or VPB2 */ \ reg32 = reg32 | (1<<23); /* Enable UART1 RXD1 or VPB1 */ \ reg32 = reg32 | (1<<22); /* Enable UART1 TXD1 or VPB0 */ \ reg32 = reg32 | (1<<21); /* Enable UART1 NRTS1 or VPCLK */ \ reg32 = reg32 | (1<<20); /* Enable UART1 NDTR1 or VPVS */ \ reg32 = reg32 | (1<<19); /* Enable UART1 NRI1 or VPHS */ \ reg32 = reg32 | (1<<18); /* Enable UART1 NDSR1 or VPODD */ \ reg32 = reg32 | (1<<17); /* Enable UART1 NDCD1 or VPDE */ \ reg32 = reg32 | (1<<16); /* Enable UART1 NCTS1 */ \ *((volatile u_long *) 0x1e6e2084) = reg32; \ \ /* SCU88 Multi-function Pin Control #3 = 0x01000000 => 0x00000000 */ \ reg32 = *((volatile u_long *) 0x1e6e2088); \ /*reg32 = reg32 | (1<<31); Enable MAC#1 MDIO1 */ \ /*reg32 = reg32 | (1<<30); Enable MAC#1 MDC1 */ \ reg32 = reg32 | (1<<29); /* Enable SPI2MISO */ \ reg32 = reg32 | (1<<28); /* Enable SPI2MOSI */ \ reg32 = reg32 | (1<<27); /* Enable SPI2CK */ \ reg32 = reg32 | (1<<26); /* Enable SPI2CS0 */ \ reg32 = reg32 & ~(1<<25); /* Enable flash FWSPICS2# */ \ reg32 = reg32 & ~(1<<24); /* Enable flash FWSPICS1# */ \ reg32 = reg32 | (1<<7); /* Enable PWM7 or VPG7 */ \ reg32 = reg32 | (1<<6); /* Enable PWM6 or VPG6 */ \ reg32 = reg32 | (1<<5); /* Enable PWM5 or VPG5 */ \ reg32 = reg32 | (1<<4); /* Enable PWM4 or VPG4 */ \ reg32 = reg32 | (1<<3); /* Enable PWM3 or VPG3 */ \ reg32 = reg32 | (1<<2); /* Enable PWM2 or VPG2 */ \ reg32 = reg32 | (1<<1); /* Enable PWM1 or VPG1 */ \ reg32 = reg32 | (1<<0); /* Enable PWM0 or VPG0 */ \ *((volatile u_long *) 0x1e6e2088) = reg32; \ \ \ /* SCU90 Multi-function Pin Control #5 = 0x00000000 => 0x007F0004 */ \ reg32 = *((volatile u_long *) 0x1e6e2090); \ /*reg32 = reg32 & ~(1<<31); Enable Parallel NOR */ \ /*reg32 = reg32 & ~(1<<30); Enable LPC Plus Interface */ \ /*reg32 = reg32 & ~(1<<29); Enable USB2.0 Host port#1 */ \ /*reg32 = reg32 & ~(1<<28); Reserved */ \ reg32 = reg32 | (1<<27); /* Enable I2C14 function pins */ \ reg32 = reg32 | (1<<26); /* Enable I2C13 function pins */ \ reg32 = reg32 | (1<<25); /* Enable I2C12 function pins */ \ reg32 = reg32 | (1<<24); /* Enable I2C11 function pins */ \ reg32 = reg32 | (1<<23); /* Enable I2C10 function pins */ \ reg32 = reg32 | (1<<22); /* Enable I2C9 function pins */ \ reg32 = reg32 | (1<<21); /* Enable I2C8 function pins */ \ reg32 = reg32 | (1<<20); /* Enable I2C7 function pins */ \ reg32 = reg32 | (1<<19); /* Enable I2C6 function pins */ \ reg32 = reg32 | (1<<18); /* Enable I2C5 function pins */ \ reg32 = reg32 | (1<<17); /* Enable I2C4 function pins */ \ reg32 = reg32 | (1<<16); /* Enable I2C3 function pins */ \ /*reg32 = reg32 | (1<<15); RGMII2/RMII2 RX pins internal pull down resistor disable */ \ /*reg32 = reg32 | (1<<14); RGMII2/RMII2 RX pins internal pull down resistor disable */ \ /*reg32 = reg32 & ~(1<<13); RGMII1/RMII1 RX pins internal pull down resistor disable */ \ /*reg32 = reg32 & ~(1<<12); RGMII1/RMII1 RX pins internal pull down resistor disable */ \ \ /* \ * RMII IO driving strength \ * 00: 20pF loading \ * 01: 40pF loading \ * 10: 60pF loading \ * 11: 75pF loading \ */ \ /*reg32 = reg32 & ~(1<<11); RMII2 IO driving strength */ \ /*reg32 = reg32 & ~(1<<10); RMII2 IO driving strength */ \ /*reg32 = reg32 | (1<<9); RMII1 IO driving strength */ \ /*reg32 = reg32 | (1<<8); RMII1 IO driving strength */ \ \ /*reg32 = reg32 & ~(1<<7); Enable UART6 function pins */ \ /*reg32 = reg32 & ~(1<<6); Reserved, must keep at value '0' */ \ \ /* \ * Enable digital video function pins \ * 0x: disable \ * 01: 24 bits (R8/G8/B8) dual edge video mode \ * 11: reserved \ */ \ /*reg32 = reg32 & ~(1<<5); Enable digital video function pins */ \ /*reg32 = reg32 & ~(1<<4); Enable digital video function pins */ \ \ /*reg32 = reg32 & ~(1<<3); Enable SD1 port 8 bits mode */ \ reg32 = reg32 | (1<<2); /* Enable MAC#2 MDC2/MDIO2 function pins */ \ reg32 = reg32 | (1<<1); /* Enable SD2 function pins */ \ reg32 = reg32 & ~(1<<0); /* Enable SD1 function pins */ \ *((volatile u_long *) 0x1e6e2090) = reg32; \ \ /* SCUA0 Control #7 */ \ reg32 = *((volatile u_long *) 0x1e6e20A0); \ reg32 = reg32 | (1<<13); /* Enable GPIOU5*/ \ /*reg32 = reg32 | (1<<5); Enable GPIOT4*/ \ /*reg32 = reg32 | (1<<4); Enable GPIOT5*/ \ reg32 = reg32 | (1<<0); /* Enable GPIOT0*/ \ *((volatile u_long *) 0x1e6e20A0) = reg32; \ \ /* SCUA4 Control #8 */ \ reg32 = *((volatile u_long *) 0x1e6e20A4); \ reg32 = reg32 | (1<<25); /* Enable SALT8*/ \ *((volatile u_long *) 0x1e6e20A4) = reg32; \ \ /* config GPIO data and direction */ \ *(volatile ulong *) (0x1e780000 + 0x00) = 0x0000BE0C; /* Data: GPIOD, GPIOC, GPIOB, GPIOA */ \ *(volatile ulong *) (0x1e780000 + 0x04) = 0x00002001; /* Dir : GPIOD, GPIOC, GPIOB, GPIOA */ \ \ /* config extend GPIO data and direction */ \ *(volatile ulong *) (0x1e780000 + 0x20 + 0x00) = 0x00FFBFFF; /* Data: GPIOH, GPIOG, GPIOF, GPIOE */\ *(volatile ulong *) (0x1e780000 + 0x20 + 0x04) = 0xFF08022A; /* Dir : GPIOH, GPIOG, GPIOF, GPIOE */\ \ /* config simple GPIO 0 data and direction */ \ *(volatile ulong *) (0x1e780000 + 0x70 + 0x00) = 0x000000FF; /* Data: GPIOL, GPIOK, GPIOJ, GPIOI */\ *(volatile ulong *) (0x1e780000 + 0x70 + 0x04) = 0x00000000; /* Dir : GPIOL, GPIOK, GPIOJ, GPIOI */\ \ /* config simple GPIO 1 data and direction */ \ *(volatile ulong *) (0x1e780000 + 0x78 + 0x00) = 0x00000029; /* Data: GPIOP, GPIOO, GPION, GPIOM */\ *(volatile ulong *) (0x1e780000 + 0x78 + 0x04) = 0x00000000; /* Dir : GPIOP, GPIOO, GPION, GPIOM */\ \ /* config simple GPIO 2 data and direction */ \ *(volatile ulong *) (0x1e780000 + 0x80 + 0x00) = 0x01FE03C0; /* Data: GPIOT, GPIOS, GPIOR, GPIOQ */\ *(volatile ulong *) (0x1e780000 + 0x80 + 0x04) = 0x01F20000; /* Dir : GPIOT, GPIOS, GPIOR, GPIOQ */\ \ /* config simple GPIO data and direction */ \ *(volatile ulong *) (0x1e780000 + 0x88 + 0x00) = 0x00000020; /* Data: GPIOX, GPIOW, GPIOV, GPIOU */\ \ /* config simple GPIO data and direction */ \ *(volatile ulong *) (0x1e780000 + 0x1E0 + 0x00) = 0x05FE0E0F; /* Data:GPIOAB, GPIOAA, GPIOZ, GPIOY*/\ *(volatile ulong *) (0x1e780000 + 0x1E0 + 0x04) = 0x0000FD00; /* Dir :GPIOAB, GPIOAA, GPIOZ, GPIOY*/\ \ /* set snooping address#0 as 80h, and enable snooping address#0 */ \ reg32 = *((volatile u_long *) 0x1e789090); \ *((volatile u_long *) 0x1e789090) = (reg32 & 0xFFFF0000) | 0x00000080; \ reg32 = *((volatile u_long *) 0x1e789080); \ *((volatile u_long *) 0x1e789080) = reg32 | 0x00000001; \ \ /* set command source of GPIOH to LPC */ \ reg32 = *((volatile u_long *) 0x1e780068); \ *((volatile u_long *) 0x1e780068) = reg32 | 0x01000000; \ reg32 = *((volatile u_long *) 0x1e78006C); \ *((volatile u_long *) 0x1e78006C) = reg32 & 0xFEFFFFFF; \ \ /* set clock division and period of type M/N , now PWM driver init first */ \ *((volatile ulong *) 0x1e786004) = 0xFF11FF11; \ \ /* CVE 2019-6260 Setting */ \ /* set HICR5 bit 8 and 10 to 0 */ \ reg32 = *((volatile u_long *) 0x1e789080); \ *((volatile u_long *) 0x1e789080) = reg32 & 0xFFFFFAFF; \ \ /* set HICRB to disable SIO iLPC2AHB function */ \ reg32 = *((volatile u_long *) 0x1e789100); \ *((volatile u_long *) 0x1e789100) = reg32 | 0x00000040; \ \ /* set SCU70 HW Strap bit 20 to 0 */ \ /* By setting SCU7C HW Strap bit 20 to 1 */ \ reg32 = *((volatile u_long *) 0x1e6e207c); \ *((volatile u_long *) 0x1e6e207c) = reg32 | 0x00100000; \ \ /* set SCU180 bit 1, 6, 14 to 0 */ \ reg32 = *((volatile u_long *) 0x1e6e2180); \ *((volatile u_long *) 0x1e6e2180) = reg32 & 0xFFFFBFBD; \ \ /* set SCU2C bit 0 and 10 to 1 */ \ reg32 = *((volatile u_long *) 0x1e6e202c); \ *((volatile u_long *) 0x1e6e202c) = reg32 | 0x00000401; \ \ /* set SCU04 bit 25 to 1 */ \ reg32 = *((volatile u_long *) 0x1e6e2004); \ *((volatile u_long *) 0x1e6e2004) = reg32 | 0x02000000; \ /* End of CVE 2019-6260 Setting */ \ \ /* set PWM duty cycle to 90%, now PWM driver init first */ \ *((volatile ulong *) 0x1e786008) = 0xFE00FE00; /*PWM B, PWM A */ \ *((volatile ulong *) 0x1e78600C) = 0xFE00FE00; /*PWM D, PWM C */ \ *((volatile ulong *) 0x1e786048) = 0xFE00FE00; /*PWM F, PWM E */ \ *((volatile ulong *) 0x1e78604C) = 0xFE00FE00; /*PWM H, PWM G */ \ *((volatile ulong *) 0x1e786000) = 0xFFFF0F01; /*enable PWM, and set PWM A/B/C/D to type M */ \ *((volatile ulong *) 0x1e786040) = 0x00000F00; /*enable PWM, and set PWM E/F/G/H to type M */ \ /* SCU00 Protection Key Register */ \ *((volatile u_long *) 0x1e6e2000) = 0x0; /* lock SCU register*/ \ printf("QUANTA_OEM_INIT Complete!\n"); \ } while(0) #endif