--- uboot/arch/arm/cpu/arm1176/ast2500/platform.S.old 2017-11-16 13:39:45.223778970 +0800 +++ uboot/arch/arm/cpu/arm1176/ast2500/platform.S 2017-11-16 14:33:39.843857292 +0800 @@ -17,8 +17,8 @@ * * Gary Hsu, * - * Version : 16 - * Release date: 2017.06.19 + * Version : 18 + * Release date: 2017.10.27 * * Priority of fix item: * [P1] = critical @@ -64,8 +64,8 @@ * | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0 * | : 4.[P2] Modify read timing margin report policy, change DDR4 min value from 0.35 to 0.3. Add "Warning" while violated. * V13|2016.08.29 : 1.[P3] Add option to route debug message output port from UART5 to UART1 - * |2016.09.02 : 3.[P2] Add range control for cache function when ECC enabled - * |2016.09.06 : 2.[P1] Enable full mask setting for first SOC reset, since the coverage of original default setting is not enough + * |2016.09.02 : 2.[P2] Add range control for cache function when ECC enabled + * |2016.09.06 : 3.[P1] Enable full mask setting for first SOC reset, since the coverage of original default setting is not enough * V14|2016.10.25 : 1.[P2] Change Ron manual calibration to default OFF, customer can enable it to do fine-tuning of the Vix issue * |2016.11.07 : 2.[P3] Add log information of DDR4 PHY Vref training * V15|2017.04.06 : 1.[P1] Modify USB portA initial sequence, this is to prevent DMA lock condition of USB Virtual Hub device for some chips. @@ -75,12 +75,16 @@ * |2017.06.19 : 3.[P2] Add initial sequence for LPC controller * |2017.06.19 : 4.[P2] Add initial full-chip reset option * |2017.06.19 : 5.[P3] Add 10ms delay after DDR reset + * V17|2017.09.25 : 1.[P1] Modify DDR4 side ODT value from 60ohm to 48ohm. + * |2017.09.25 : 2.[P1] Add Hynix DDR4 frequency slow down option. + * V18|2017.10.26 : 1.[P3] Include the modification of DDR4 side ODT value in V17 into the option of Hynix DDR4 configuration. + * |2017.10.26 : 2.[P2] Enhance initial sequence for LPC controller * Note: Read timing report is only a reference, it is not a solid rule for stability. * * Optional define variable - * 1. DRAM Speed // - * CONFIG_DRAM_1333 // - * CONFIG_DRAM_1600 // (default) + * 1. DRAM Speed // + * CONFIG_DRAM_1333 // + * CONFIG_DRAM_1600 // (default) * 2. ECC Function enable * CONFIG_DRAM_ECC // define to enable ECC function * CONFIG_DRAM_ECC_SIZE // define the ECC protected memory size @@ -88,16 +92,19 @@ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200 * CONFIG_DRAM_UART_TO_UART1 // route UART5 to UART port1 * 4. DRAM Type - * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die - * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part + * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die + * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part * 5. Firmware 2nd boot flash * CONFIG_FIRMWARE_2ND_BOOT (Removed) * 6. Enable DRAM extended temperature range mode * CONFIG_DRAM_EXT_TEMP - * 7. UART5 message output // - * FEATURE_DRAM_INIT_UART_38400 // add radio button in PRJ - * FEATURE_DRAM_INIT_UART_57600 - * FEATURE_DRAM_INIT_UART_115200 + * 7. Select WDT_Full mode for power up initial reset + * ASTMMC_INIT_RESET_MODE_FULL + * 8. Hynix DDR4 options + * CONFIG_DDR4_SUPPORT_HYNIX // Enable this when Hynix DDR4 included in the BOM + * CONFIG_DDR4_HYNIX_SET_1536 + * CONFIG_DDR4_HYNIX_SET_1488 + * CONFIG_DDR4_HYNIX_SET_1440 // Default ****************************************************************************** */ @@ -110,8 +117,8 @@ Free registers: r0, r1, r2, r3, r6, r7, r8, r9, r10, r11 ******************************************************************************/ -#define ASTMMC_INIT_VER 0x10 @ 8bit verison number -#define ASTMMC_INIT_DATE 0x20170619 @ Release date +#define ASTMMC_INIT_VER 0x12 @ 8bit verison number +#define ASTMMC_INIT_DATE 0x20171027 @ Release date /****************************************************************************** BMC side DDR IO driving manual mode fine-tuning, used to improve CK/CKN Vix violation. @@ -134,6 +141,19 @@ ******************************************************************************/ //#define ASTMMC_INIT_RESET_MODE_FULL +/****************************************************************************** + There is a compatibility issue for Hynix DDR4 SDRAM. + Hynix DDR4 SDRAM is more weak on noise margin compared to Micron and Samsung DDR4. + To well support Hynix DDR4, it requlres to slow down the DDR4 operating frequency + from 1600Mbps to 1536/1488/1440 Mbps. The target frequency that can be used depends + on the MB layout. Customer can find the appropriate frequency for their products. + Below are the new defined parameters for the Hynix DDR4 supporting. + ******************************************************************************/ +#define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM +//#define CONFIG_DDR4_HYNIX_SET_1536 +//#define CONFIG_DDR4_HYNIX_SET_1488 +#define CONFIG_DDR4_HYNIX_SET_1440 + #define ASTMMC_REGIDX_010 0x00 #define ASTMMC_REGIDX_014 0x04 #define ASTMMC_REGIDX_018 0x08 @@ -214,7 +234,11 @@ .word 0x08000000 @ 0x020 .word 0x00000400 @ 0x024 .word 0x00000410 @ 0x02C - .word 0x00000101 @ 0x030 +#ifdef CONFIG_DDR4_SUPPORT_HYNIX + .word 0x00000501 @ 0x030 @ ODT = 48 ohm +#else + .word 0x00000101 @ 0x030 @ ODT = 60 ohm +#endif .word 0x00000024 @ 0x214 .word 0x03002900 @ 0x2E0 .word 0x0E0000A0 @ 0x2E4 @@ -382,6 +406,14 @@ ldr r1, [r0] ldr r0, =0x1e787008 @ read clear ldr r1, [r0] + ldr r0, =0x1e78301c @ read clear + ldr r1, [r0] + ldr r0, =0x1e78d01c @ read clear + ldr r1, [r0] + ldr r0, =0x1e78e01c @ read clear + ldr r1, [r0] + ldr r0, =0x1e78f01c @ read clear + ldr r1, [r0] ldr r0, =0x1e788020 str r2, [r0] ldr r0, =0x1e788034 @@ -613,13 +645,13 @@ /****************************************************************************** Disable WDT2 for 2nd boot function ******************************************************************************/ - +/* #ifndef CONFIG_FIRMWARE_2ND_BOOT ldr r0, =0x1e78502c mov r1, #0 str r1, [r0] #endif - +*/ /****************************************************************************** Disable WDT3 for SPI Address mode (3 or 4 bytes) detection function ******************************************************************************/ @@ -645,22 +677,49 @@ orr r1, r1, #0x40 str r1, [r0] + ldr r0, =0x1e6e2070 @ Load strap register + ldr r3, [r0] + /* Set M-PLL */ #if defined (CONFIG_DRAM_1333) ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330) #else ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396) +#if defined (CONFIG_DDR4_SUPPORT_HYNIX) + mov r1, r3, lsr #24 @ Check DDR4 + tst r1, #0x01 + beq bypass_mpll_hynix_mode_1 +#if defined (CONFIG_DDR4_HYNIX_SET_1536) + ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384) +#elif defined (CONFIG_DDR4_HYNIX_SET_1488) + ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372) +#else + ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (360) +#endif +bypass_mpll_hynix_mode_1: +#endif #endif - ldr r0, =0x1e6e2070 @ Check CLKIN = 25MHz - ldr r1, [r0] - mov r1, r1, lsr #23 + mov r1, r3, lsr #23 @ Check CLKIN = 25MHz tst r1, #0x01 beq set_MPLL #if defined (CONFIG_DRAM_1333) ldr r2, =0xC4806680 @ load PLL parameter for 25Mhz CLKIN (331) #else ldr r2, =0x930023E0 @ load PLL parameter for 25Mhz CLKIN (400) +#if defined (CONFIG_DDR4_SUPPORT_HYNIX) + mov r1, r3, lsr #24 @ Check DDR4 + tst r1, #0x01 + beq bypass_mpll_hynix_mode_2 +#if defined (CONFIG_DDR4_HYNIX_SET_1536) + ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (387.5) +#elif defined (CONFIG_DDR4_HYNIX_SET_1488) + ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (375) +#else + ldr r2, =0x93002380 @ load PLL parameter for 24Mhz CLKIN (362.5) +#endif +bypass_mpll_hynix_mode_2: +#endif #endif ldr r0, =0x1e6e2160 @ set 24M Jitter divider (HPLL=825MHz) ldr r1, =0x00011320 @@ -756,18 +815,11 @@ mov r2, r2, lsr #12 tst r2, #0x01 ldr r0, =0x1e784000 -#if defined (CONFIG_SPX_FEATURE_DRAM_INIT_UART_38400) - moveq r1, #0x27 @ Baudrate 38400 - movne r1, #0x03 @ Baudrate 38400 , div13 -#elif defined (CONFIG_SPX_FEATURE_DRAM_INIT_UART_57600) - moveq r1, #0x1A @ Baudrate 57600 - movne r1, #0x0D @ Baudrate 57600 , div13 -#elif defined (CONFIG_SPX_FEATURE_DRAM_INIT_UART_115200) - moveq r1, #0x0D @ Baudrate 115200 - movne r1, #0x01 @ Baudrate 115200, div13 -#else moveq r1, #0x0D @ Baudrate 115200 movne r1, #0x01 @ Baudrate 115200, div13 +#ifdef CONFIG_DRAM_UART_38400 + moveq r1, #0x27 @ Baudrate 38400 + movne r1, #0x03 @ Baudrate 38400 , div13 #endif str r1, [r0]