/******************************************************************************* * Copyright 2016-2018 Intel Corporation * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *******************************************************************************/ #ifndef JIT_AVX512_COMMON_CONV_KERNEL_F32_HPP #define JIT_AVX512_COMMON_CONV_KERNEL_F32_HPP #include "c_types_map.hpp" #include "memory_tracking.hpp" #include "cpu_memory.hpp" #include "jit_generator.hpp" #include "jit_primitive_conf.hpp" #include "jit_uni_eltwise.hpp" namespace mkldnn { namespace impl { namespace cpu { template struct _jit_avx512_common_conv_fwd_kernel : public jit_generator { _jit_avx512_common_conv_fwd_kernel(jit_conv_conf_t ajcp, const primitive_attr_t &attr) : jcp(ajcp), attr_(attr), eltwise_injector_(nullptr) { if (jcp.with_eltwise) eltwise_injector_ = new jit_uni_eltwise_injector_f32( this, jcp.eltwise); generate(); jit_ker_ = (void (*)(jit_conv_call_s *))getCode(); } ~_jit_avx512_common_conv_fwd_kernel() { delete eltwise_injector_; } DECLARE_CPU_JIT_AUX_FUNCTIONS(_jit_avx512_common_conv_fwd_kernel) jit_conv_conf_t jcp; const primitive_attr_t &attr_; void (*jit_ker_)(jit_conv_call_s *); private: using reg64_t = const Xbyak::Reg64; enum { typesize = sizeof(float), ker_reg_base_idx = 28, }; reg64_t param = abi_param1; reg64_t reg_inp = r8; reg64_t reg_ker = r9; reg64_t reg_out = r10; reg64_t reg_inp_prf = r11; reg64_t reg_ker_prf = r12; reg64_t reg_out_prf = r13; reg64_t reg_owb = r12; reg64_t aux_reg_inp = r14; reg64_t aux_reg_ker = r15; reg64_t aux_reg_inp_prf = rsi; reg64_t aux_reg_ker_prf = rdx; reg64_t reg_channel = rsi; reg64_t reg_bias = rdx; reg64_t aux_reg_ker_d = r9; reg64_t aux_reg_inp_d = rbx; reg64_t aux_reg_inp_d_prf = r13; reg64_t aux_reg_ker_d_prf = abi_not_param1; reg64_t reg_ki = r10; reg64_t reg_kj = rax; reg64_t reg_relu_ns = rax; reg64_t reg_oi = rbx; reg64_t reg_kh = abi_not_param1; reg64_t reg_tmp = rbp; reg64_t reg_ic_loop = rdx; reg64_t reg_inp_loop = rsi; reg64_t reg_init_flag = r13; reg64_t reg_bias_ptr = param; reg64_t aux_reg_ic = r12; reg64_t reg_binp = rax; reg64_t reg_bout = r11; reg64_t aux1_reg_inp = rbx; reg64_t aux_reg_out = abi_not_param1; reg64_t reg_long_offt = r11; reg64_t reg_out_long_offt = r14; inline Vmm vmm_ker(int i_ic) { assert(i_ic < 4); return Vmm(ker_reg_base_idx + i_ic); } inline Vmm vmm_out(int i_ur, int i_oc) { int idx = i_ur + i_oc * jcp.ur_w; assert(idx < ker_reg_base_idx); return Vmm(idx); } inline Vmm vmm_inp(int i_ic, int nb_x_blocking) { int idx = i_ic + nb_x_blocking * jcp.ur_w; assert(idx < 31); return Vmm(idx); } Xbyak::Reg64 imm_addr64 = r15; Vmm vmm_wei = Vmm(31); jit_uni_eltwise_injector_f32 *eltwise_injector_; inline void prepare_output(int ur_w); inline void store_output(int ur_w); inline void compute_loop_fma(int ur_w, int pad_l, int pad_r); inline void compute_loop_fma_core(int ur_w, int pad_l, int pad_r); inline void compute_loop_vnni(int ur_w, int pad_l, int pad_r); inline void compute_loop_4fma(int ur_w, int pad_l, int pad_r); inline void compute_loop_4fma_1st(int ur_w, int pad_l, int pad_r); inline void compute_loop(int ur_w, int pad_l, int pad_r); void generate(); inline void vadd(Vmm vmm, const Xbyak::Operand& op) { if (jcp.ver == ver_4vnni || jcp.ver == ver_vnni) vpaddd(vmm, vmm, op); else vaddps(vmm, vmm, op); } inline size_t get_output_offset(int oi, int n_oc_block) { return (size_t)jcp.typesize_out * ((size_t)n_oc_block * jcp.oh * jcp.ow * jcp.od + oi) * jcp.oc_block; } inline size_t get_input_offset(int ki, int ic, int oi, int pad_l) { size_t scale = (jcp.ver == ver_4vnni || jcp.ver == ver_vnni) ? 2 : 1; size_t iw_str = !jcp.is_1stconv ? jcp.ic_block : 1; size_t ic_str = !jcp.is_1stconv ? 1 : (size_t)jcp.iw * jcp.ih * jcp.id; return (size_t)jcp.typesize_in * ((size_t)(ki * (jcp.dilate_w + 1) + oi * jcp.stride_w - pad_l) * iw_str + scale * ic * ic_str); } inline int get_kernel_offset(int ki,int ic,int n_oc_block,int ker_number) { int scale = (jcp.ver == ver_4vnni || jcp.ver == ver_vnni) ? 2 : 1; return jcp.typesize_in * jcp.oc_block * (n_oc_block * jcp.nb_ic * jcp.ic_block * jcp.kh * jcp.kw * jcp.kd + (ic + ker_number) * scale + ki * jcp.ic_block); } inline int get_ow_start(int ki, int pad_l) { return nstl::max(0, utils::div_up(pad_l - ki * (jcp.dilate_w + 1), jcp.stride_w)); } inline int get_ow_end(int ur_w, int ki, int pad_r) { return ur_w - nstl::max(0, utils::div_up(pad_r - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1), jcp.stride_w)); } }; struct jit_avx512_common_conv_fwd_kernel { jit_avx512_common_conv_fwd_kernel(jit_conv_conf_t ajcp, const primitive_attr_t &attr) : jit_ker(nullptr), zmm_kernel_(nullptr), xmm_kernel_(nullptr) { int ch_block = ajcp.is_depthwise ? ajcp.ch_block : ajcp.oc_block; switch (ch_block) { case 16: zmm_kernel_ = new _jit_avx512_common_conv_fwd_kernel( ajcp, attr); jit_ker = zmm_kernel_->jit_ker_; return; case 4: xmm_kernel_ = new _jit_avx512_common_conv_fwd_kernel( ajcp, attr); jit_ker = xmm_kernel_->jit_ker_; return; default: assert(!"invalid channel blocking"); } } ~jit_avx512_common_conv_fwd_kernel() { delete xmm_kernel_; delete zmm_kernel_; } enum { typesize = sizeof(float) }; static bool post_ops_ok(jit_conv_conf_t &jcp, const primitive_attr_t &attr); static status_t init_conf(jit_conv_conf_t &jcp, const convolution_desc_t &cd, cpu_memory_t::pd_t &src_pd, cpu_memory_t::pd_t &weights_pd, cpu_memory_t::pd_t &dst_pd, cpu_memory_t::pd_t &bias_pd, const primitive_attr_t &attr, int nthreads); static void init_scratchpad(memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp); void(*jit_ker)(jit_conv_call_s *); _jit_avx512_common_conv_fwd_kernel *zmm_kernel_; _jit_avx512_common_conv_fwd_kernel *xmm_kernel_; }; struct jit_avx512_common_conv_bwd_data_kernel_f32: public jit_generator { jit_avx512_common_conv_bwd_data_kernel_f32(jit_conv_conf_t ajcp): jcp(ajcp) { generate(); jit_ker = (void (*)(jit_conv_call_s *))getCode(); } DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_conv_bwd_data_kernel_f32) static status_t init_conf(jit_conv_conf_t &jcp, const convolution_desc_t &cd, const memory_desc_wrapper &diff_src_d, const memory_desc_wrapper &weights_d, const memory_desc_wrapper &diff_dst_d); static void init_scratchpad(memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp); jit_conv_conf_t jcp; void (*jit_ker)(jit_conv_call_s *); private: using reg64_t = const Xbyak::Reg64; enum { typesize = sizeof(float), ker_reg_base_idx = 28, }; reg64_t param = abi_param1; reg64_t reg_dst = r8; reg64_t reg_ker = r9; reg64_t reg_src = r10; reg64_t reg_dst_prf = r11; reg64_t reg_ker_prf = r12; reg64_t reg_src_prf = r13; reg64_t aux_reg_dst = r14; reg64_t aux_reg_ker = r15; reg64_t aux_reg_dst_prf = rsi; reg64_t aux_reg_ker_prf = rdx; reg64_t aux_reg_dst_d_prf = r13; reg64_t aux_reg_dst_d = rbx; reg64_t aux_reg_ker_d_prf = abi_not_param1; reg64_t aux_reg_ker_d = r9; reg64_t reg_ki = r10; reg64_t reg_kj = rax; reg64_t reg_oi = rbx; reg64_t reg_kh = abi_not_param1; reg64_t reg_channel = rsi; reg64_t reg_tmp = rbp; reg64_t reg_long_offt = r14; inline Xbyak::Zmm zmm_ker(int i_ic) { assert(i_ic < 4); return Xbyak::Zmm(ker_reg_base_idx + i_ic); } inline Xbyak::Zmm zmm_inp(int i_ic, int nb_x_blocking) { int idx = i_ic + nb_x_blocking * jcp.ur_w; assert(idx < 31); return Xbyak::Zmm(idx); } inline Xbyak::Zmm zmm_out(int i_ur, int i_oc) { int idx = i_ur + i_oc * jcp.ur_w; assert(idx < ker_reg_base_idx); return Xbyak::Zmm(idx); } inline void vpXdpwssd(Xbyak::Zmm zmm1, Xbyak::Zmm zmm2, reg64_t reg, int offset) { if (jcp.ver == ver_4vnni) vp4dpwssd(zmm1, zmm2, EVEX_compress_addr(reg, offset, false)); else vpdpwssd(zmm1, zmm2, EVEX_compress_addr(reg, offset, true)); } inline void vadd(Xbyak::Zmm zmm, const Xbyak::Operand& op) { if (jcp.ver == ver_4vnni || jcp.ver == ver_vnni) vpaddd(zmm, zmm, op); else vaddps(zmm, zmm, op); } Xbyak::Zmm zmm_wei = Xbyak::Zmm(31); inline void prepare_output(int ur_w); inline void store_output(int ur_w); inline void compute_loop_4fma(int ur_w, int l_overflow, int r_overflow); inline void compute_loop_vnni(int ur_w, int l_overflow, int r_overflow); inline void compute_loop_fma(int ur_w, int l_overflow, int r_overflow); inline void compute_loop_fma_core(int ur_w, int l_overflow, int r_overflow); inline void compute_loop(int ur_w, int l_overflow, int r_overflow); void generate(); inline int get_iw_start(int ki, int l_overflow) { int res = (jcp.iw - 1 + jcp.r_pad) % jcp.stride_w + l_overflow * jcp.stride_w - (jcp.kw - 1 - ki) * (jcp.dilate_w + 1); while (res < 0) res += jcp.stride_w; return res; } inline int get_iw_end(int ur_w, int ki, int r_overflow) { if (utils::one_of(ur_w, jcp.iw, jcp.ur_w_tail)) ur_w += nstl::min(0, jcp.r_pad); // remove negative padding int res = (ur_w - 1 + jcp.l_pad) % jcp.stride_w + r_overflow * jcp.stride_w - ki * (jcp.dilate_w + 1); while (res < 0) res += jcp.stride_w; return ur_w - res; } }; struct jit_avx512_common_conv_bwd_weights_kernel_f32 : public jit_generator { jit_avx512_common_conv_bwd_weights_kernel_f32(jit_conv_conf_t ajcp) : jcp(ajcp) { generate(); jit_ker = (void (*)(jit_conv_call_s *))getCode(); } DECLARE_CPU_JIT_AUX_FUNCTIONS(jit_avx512_common_conv_bwd_weights_kernel_f32) static status_t init_conf(jit_conv_conf_t &jcp, const convolution_desc_t &cd, cpu_memory_t::pd_t &src_pd, cpu_memory_t::pd_t &diff_weights_pd, cpu_memory_t::pd_t &diff_bias_pd, cpu_memory_t::pd_t &diff_dst_pd); static void init_scratchpad(memory_tracking::registrar_t &scratchpad, const jit_conv_conf_t &jcp); jit_conv_conf_t jcp; void (*jit_ker)(jit_conv_call_s *); private: using reg64_t = const Xbyak::Reg64; enum {typesize = sizeof(float)}; static const int max_ur_w; static const int min_oh_reduce; reg64_t param = abi_param1; reg64_t reg_input = rax; reg64_t reg_kernel = rdx; reg64_t reg_output = rsi; reg64_t b_ic = abi_not_param1; reg64_t kj = r8; reg64_t reg_kh = r9; reg64_t reg_ur_w_trips = r10; reg64_t reg_oj = r15; reg64_t reg_ih_count = rbx; reg64_t reg_tmp = r14; reg64_t reg_long_offt = r14; reg64_t ki = r11; reg64_t reg_kd_count = r12; reg64_t reg_oi = r12; reg64_t reg_d_index = r13; reg64_t reg_input_d = r15; reg64_t reg_output_d = rbx; reg64_t aux_reg_input = r12; reg64_t aux_reg_kernel = r13; reg64_t reg_bias = rbx; inline void bias_kernel_2d(); inline void bias_kernel_3d(); inline void maybe_zero_kernel(); inline void compute_oh_step_unroll_ow_icblock(int ic_block_step, int max_ur_w); inline void od_step_comeback_pointers(); inline void oh_step_comeback_pointers(); inline void compute_oh_step_unroll_ow(int ic_block_step, int max_ur_w); inline void compute_ic_block_step(int ur_w, int pad_l, int pad_r, int ic_block_step, int input_offset, int kernel_offset, int output_offset, bool input_wraparound = false); inline void compute_ic_block_step_fma(int ur_w, int pad_l, int pad_r, int ic_block_step, int input_offset, int kernel_offset, int output_offset, bool input_wraparound); inline void compute_ic_block_step_4fma(int ur_w, int pad_l, int pad_r, int ic_block_step, int input_offset, int kernel_offset, int output_offset, bool input_wraparound); inline void compute_ic_block_step_vnni(int ur_w, int pad_l, int pad_r, int ic_block_step, int input_offset, int kernel_offset, int output_offset, bool input_wraparound); inline void compute_oh_step_common(int ic_block_step, int max_ur_w); inline void compute_oh_step_disp(); inline void compute_oh_loop_common(); inline void compute_oh_loop_partial(); inline void compute_od_loop_partial(); inline bool compute_full_spat_loop(); inline bool flat_4ops_compute(); inline void compute_loop(); void generate(); static void balance(const jit_conv_conf_t &j, int &nthr, int &nthr_mb, int &nthr_g, int &nthr_oc_b, int &nthr_ic_b); }; } } } #endif