/******************************************************************************* NAME $RCSfile: commMEC.h,v $ SUMMARY MEC code for PikesPeak VERSION $Revision: 1.21 $ UPDATE DATE $Date: 2010/02/22 10:48:19 $ PROGRAMMER $Author: jim $ Copyright 2009 LSI Corporation. All Rights Reserved. DESCRIPTION: Define Model, Component, Item and Error code for PikesPeak. REFERENCE: *******************************************************************************/ #ifndef __INCcommMEC #define __INCcommMEC /* Model Code */ #define MODEL_CODE_TEMP 0x0000 /*Component Code */ #define MEC_COMP_CODE_TEMP 0x0000 #define MEC_PATSBURG 0x0000 #define MEC_MEM 0x2100 #define MEC_DMA 0x2200 #define MEC_NVSRAM 0x3300 #define MEC_RTC 0x3900 #define MEC_LED 0x4200 #define MEC_PSOC 0x5610 #define MEC_FPGA 0x5700 #define MEC_BBU 0x5830 #define MEC_PCIE_SWITCH 0x4300 #define MEC_NIC82576_0 0x44C0 #define MEC_NIC82576_1 0x44C1 #define MEC_NIC82579 0x44C3 #define MEC_I2C 0x5820 #define MEC_TEMP_SENSOR 0x5840 #define MEC_GEN_BUS_ERROR 0x8000 #define MEC_LSI_2008_BASE_DC 0x6D10 #define MEC_SAS_EXPANDER 0x6D30 /********************************************************* * Generic PCI register test *********************************************************/ /* Item */ #define PCI_READ_TEST 1 #define PCI_ADDR_LINE_TEST 2 #define PCI_DATA_LINE_TEST 3 #define PCI_REGISTER_TEST 4 /* Error code*/ #define PCI_ERROR_CODE_1 1 #define PCI_ERROR_CODE_2 2 #define PCI_ERROR_CODE_3 3 #define PCI_ERROR_CODE_4 4 #define PCI_ERROR_CODE_5 5 #define PCI_ERROR_CODE_6 6 #define PCI_ERROR_CODE_7 7 /* Description Message */ #define PCI_ERROR_MSG_1 "[PCI_READ_TEST] wrong initial register value" #define PCI_ERROR_MSG_2 "[PCI_READ_TEST] wrong reserved register value" #define PCI_ERROR_MSG_3 "[PCI_ADDRLINE_TEST] failed (RO)" #define PCI_ERROR_MSG_4 "[PCI_ADDRLINE_TEST] failed (RWC)" #define PCI_ERROR_MSG_5 "[PCI_ADDRLINE_TEST] failed (RW)" #define PCI_ERROR_MSG_6 "[PCI_DATALINE_TEST] failed" #define PCI_ERROR_MSG_7 "[PCI_REGISTER_TEST] failed to find pci device" /********************************************************* * * Crystal Beach DMA **********************************************************/ /* Item */ #define DMA_DIAG_ITEM_CODE_REGISTER 1 #define DMA_DIAG_ITEM_CODE_INTERRUPT 2 #define DMA_DIAG_ITEM_CODE_MEMBLKFILL 3 #define DMA_DIAG_ITEM_CODE_TRANSFER 4 #define DMA_DIAG_ITEM_CODE_CRC_GEN 5 #define DMA_DIAG_ITEM_CODE_XOR_GEN 6 #define DMA_DIAG_ITEM_CODE_PQ_GEN 7 #define DMA_DIAG_ITEM_CODE_BOARD_STRESS_XOR 8 #define DMA_DIAG_ITEM_CODE_BOARD_STRESS_COPY 9 /* Error code*/ #define DMA_DIAG_ERROR_CODE_KMALLOC_FAILED 1 #define DMA_DIAG_ERROR_CODE_EXECTION_FAILED 2 #define DMA_DIAG_ERROR_CODE_TEST_INCOMPLETE 3 #define DMA_DIAG_ERROR_CODE_PCI_REG_ERR 4 #define DMA_DIAG_ERROR_CODE_MM_REGISTER_ERR 5 #define DMA_DIAG_ERROR_CODE_INTERRUPT_ERR 6 #define DMA_DIAG_ERROR_CODE_MEMBLKFILL_ERR 7 #define DMA_DIAG_ERROR_CODE_TRANSFER_ERR 8 #define DMA_DIAG_ERROR_CODE_CRC_GEN_ERR 9 #define DMA_DIAG_ERROR_CODE_XOR_GEN_ERR 10 #define DMA_DIAG_ERROR_CODE_XOR_VERIFY_ERR 11 #define DMA_DIAG_ERROR_CODE_XOR_BAD_PARITY_ERR 12 #define DMA_DIAG_ERROR_CODE_PQ_GEN_ERR 13 #define DMA_DIAG_ERROR_CODE_PQ_VERIFY_ERR 14 #define DMA_DIAG_ERROR_CODE_PQ_BAD_PARITY_ERR 15 #define DMA_DIAG_ERROR_CODE_BS_RESOURCE_FAILED 16 #define DMA_DIAG_ERROR_CODE_EXECTION_TIMEOUT 17 /* Description Message */ #define DMA_DIAG_ERROR_MSG_KMALLOC_FAILED "kernel resource allocation failed" #define DMA_DIAG_ERROR_MSG_EXECTION_FAILED "DMA execution failed" #define DMA_DIAG_ERROR_MSG_TEST_INCOMPLETE "Incomplete Test" #define DMA_DIAG_ERROR_MSG_PCI_DEV_ERR "PCI device detect error" #define DMA_DIAG_ERROR_MSG_PCI_REG_RD_ERR "PCI register read error" #define DMA_DIAG_ERROR_MSG_PCI_REG_AD_ERR "PCI register address line error" #define DMA_DIAG_ERROR_MSG_PCI_REG_DL_ERR "PCI register data line error" #define DMA_DIAG_ERROR_MSG_MM_REG_RD_ERR "Memory-Mapping Register Test read failed" #define DMA_DIAG_ERROR_MSG_MM_REG_WR_ERR "Memory-Mapping Register Test write failed" #define DMA_DIAG_ERROR_MSG_INTERRUPT_ERR "Interrupt Test failed" #define DMA_DIAG_ERROR_MSG_MEMBLKFILL_ERR "Memory Block Fill Test failed" #define DMA_DIAG_ERROR_MSG_MEMBLKFILLZERO_ERR "Memory Block Fill with Zero Test failed" #define DMA_DIAG_ERROR_MSG_TRANSFER_ERR "Memory Block Transfer Test failed" #define DMA_DIAG_ERROR_MSG_CRC_GEN_ERR "CRC32C Generation Test failed" #define DMA_DIAG_ERROR_MSG_XOR_GEN_ERR "XOR Generation Test failed" #define DMA_DIAG_ERROR_MSG_XOR_VERIFY_ERR "XOR Verification Test failed" #define DMA_DIAG_ERROR_MSG_XOR_BAD_PARITY_ERR "XOR Generation Fault Inject Test Failed" #define DMA_DIAG_ERROR_MSG_PQ_GEN_P_ERR "PQ Generation P Test failed" #define DMA_DIAG_ERROR_MSG_PQ_GEN_Q_ERR "PQ Generation Q Test failed" #define DMA_DIAG_ERROR_MSG_PQ_VERIFY_ERR "PQ Verification Test failed" #define DMA_DIAG_ERROR_MSG_PQ_BAD_PARITY_ERR "PQ Generation Bad Parity Detection Failed" #define DMA_DIAG_ERROR_MSG_BS_RESOURCE_FAILED "Board Stress Test Allocation Failed" #define DMA_DIAG_ERROR_MSG_BS_MEM_ADDR_ERR "Board Stress Invalid Memory Testing Address" #define DMA_DIAG_ERROR_MSG_EXECTION_TIMEOUT "DMA execution timeout" /********************************************************* * DDR3 SDRAM *********************************************************/ /* Item Code */ #define MEM_DIAG_ITEM_CODE_DATALINES 0x01 #define MEM_DIAG_ITEM_CODE_ADDRESSLINES 0x02 #define MEM_DIAG_ITEM_CODE_BYTEENABLE 0x03 #define MEM_DIAG_ITEM_CODE_MARCHC 0x04 #define MEM_DIAG_ITEM_CODE_EXTENDPATTERNS 0x05 #define MEM_DIAG_ITEM_CODE_ADMAOPERATION 0x06 #define MEM_DIAG_ITEM_CODE_PSEUDORANDOMPATTERNS 0x07 #define MEM_DIAG_ITEM_CODE_ECCTEST 0x08 /* Error Code */ #define MEM_DIAG_ERROR_CODE_BAD_DL 0x01 #define MEM_DIAG_ERROR_CODE_BAD_AL 0x02 #define MEM_DIAG_ERROR_CODE_BAD_BL 0x03 #define MEM_DIAG_ERROR_CODE_DATA_VERIFY_ERR 0x04 #define MEM_DIAG_ERROR_CODE_ECC_SB_ERR_NOT_CORR 0x05 #define MEM_DIAG_ERROR_CODE_ECC_MB_ERR_ON_SB_TEST 0x06 #define MEM_DIAG_ERROR_CODE_ECC_SB_ERR_NOT_DET 0x07 #define MEM_DIAG_ERROR_CODE_ECC_MB_ERR_NOT_DET 0x08 #define MEM_DIAG_ERROR_CODE_ECC_SB_SYN_CHK_NOT_CORR 0x09 #define MEM_DIAG_ERROR_CODE_ECC_ERR_NOT_DET_CORR 0x0A #define MEM_DIAG_ERROR_CODE_ECC_DMA_TRANSACTION_FAIL 0x0B #define MEM_DIAG_ERROR_CODE_INPUT_PARAMS_INVALID 0x0C #define MEM_DIAG_ERROR_CODE_IOREMAP_FAILED 0x0D #define MEM_DIAG_ERROR_CODE_DMA_FAILED 0x0E #define MEM_DIAG_ERROR_CODE_UNKNOW_REASON 0x1F /* Error Message Description*/ #define MEM_DIAG_ERROR_MSG_BAD_DL "Bad data line" #define MEM_DIAG_ERROR_MSG_BAD_AL "Bad address line" #define MEM_DIAG_ERROR_MSG_BAD_BL "Bad byte-enable line" #define MEM_DIAG_ERROR_MSG_DATA_VERIFY_ERR "Data validation error" #define MEM_DIAG_ERROR_MSG_ECC_SB_ERR_NOT_CORR "Single bit error not corrected" #define MEM_DIAG_ERROR_MSG_ECC_MB_ERR_ON_SB_TEST "Multi-bit error detected during single bit test" #define MEM_DIAG_ERROR_MSG_ECC_SB_ERR_NOT_DET "Single bit error not detected" #define MEM_DIAG_ERROR_MSG_ECC_MB_ERR_NOT_DET "Multi-bit error not detected" #define MEM_DIAG_ERROR_MSG_ECC_SB_SYN_CHK_NOT_CORR "Syndorme not checked correctly on single bit error" #define MEM_DIAG_ERROR_MSG_ECC_ERR_NOT_DET_CORR "ECC error not detected correctly" #define MEM_DIAG_ERROR_MSG_ECC_DMA_TRANSACTION_FAIL "Data transaction failed by ADMA after inject ECC error" #define MEM_DIAG_ERROR_MSG_INPUT_PARAMS_INVALID "Invalid parameters input" #define MEM_DIAG_ERROR_MSG_IOREMAP_FAILED "Kernel ioremap failed" #define MEM_DIAG_ERROR_MSG_DMA_FAILED "crystal beach dma failed" #define MEM_DIAG_ERROR_MSG_UNKNOW_REASON "Memories diagnostic found error but unknown reason" /********************************************************* * PSOC *********************************************************/ /* Item */ #define PSOC_ID_IN_MEC 0x01 #define PSOC_ID_OUT_MEC 0x02 /* Error Code */ #define PSOC_UUT_BOARD_ID_ERROR 0x0001 #define PSOC_FIXTURE_BOARD_ID_ERROR 0x0002 /* Error Message */ #define MSG_PSOC_UUT_BOARD_ID_ERROR "UUT Board ID Out : Failed." #define MSG_PSOC_FIXTURE_BOARD_ID_ERROR "Fixture Board ID In : Failed." /********************************************************* * FPGA *********************************************************/ /* Item */ #define FPGA_PCI_REG_MEC 0x01 #define FPGA_ID_READ_MEC 0x02 #define FPGA_I2C_MEC 0x03 #define FPGA_LED_MEC 0x04 #define FPGA_CROSS_MEC 0x05 #define FPGA_EPP_MEC 0x06 #define FPGA_NVSRAM_LOCK_MEC 0x07 #define FPGA_DRIVE_INPLACE_MEC 0x08 #define FPGA_MISCELLANEOUS_MEC 0x09 #define FPGA_BBU_PS_MEC 0x0A #define FPGA_PROTECTED_WRITE_REGISTER_MEC 0x0B #define FPGA_PROGRAM_INTERFACE_MEC 0x0C #define FPGA_SWITCH_BUFFER_MEC 0x0D #define FPGA_INTERRUPT_MEC 0x4A #define FPGA_RESET_MEC 0x4B #define FPGA_CWT_MEC 0x4C #define FPGA_DRIVE_CONNECTION_TEST_A_MEC 0x51 #define FPGA_DRIVE_CONNECTION_TEST_B_MEC 0x52 #define FPGA_DRIVE_CONNECTION_TEST_C_MEC 0x53 #define FPGA_MIDPLANE_LED_MEC 0x54 #define FPGA_MIDPLANE_UART_MEC 0x55 #define FPGA_MIDPLANE_I2C_MEC 0x56 #define FPGA_MIDPLANE_PSOC_MEC 0x57 #define FPGA_MIDPLANE_MISCELLANEOUS_MEC 0x58 /****************************/ /* ID Read Error Code, 0x02 */ #define FPGA_ID_GOOD 0x0000 #define FPGA_BOARD_ID_ERROR 0x0001 #define FPGA_SUBSYSTEM_ID_INFORMATION_ERROR 0x0002 #define FPGA_ALTERNATE_BOARD_ID_ERROR 0x0003 #define FPGA_HOST_BOARD_ID_ERROR 0x0004 #define FPGA_ALTERNATE_HOST_BOARD_ID_ERROR 0x0005 #define FPGA_FPGA_REVISION_ERROR 0x0006 #define FPGA_FPGA_DEVICE_ID_ERROR 0x0007 /* IDs Read Test Description Message */ #define MSG_FPGA_ID_GOOD "IDs Read : Good." #define MSG_FPGA_BOARD_ID_ERROR "Board ID : Failed." #define MSG_FPGA_SUBSYSTEM_ID_INFORMATION_ERROR "Subsystem ID Information : Failed." #define MSG_FPGA_ALTERNATE_BOARD_ID_ERROR "Alternate Board ID : Failed." #define MSG_FPGA_HOST_BOARD_ID_ERROR "Host Card ID : Failed." #define MSG_FPGA_ALTERNATE_HOST_BOARD_ID_ERROR "Alternate Host Card ID : Failed." #define MSG_FPGA_FPGA_REVISION_ERROR "FPGA Revision : Failed." #define MSG_FPGA_FPGA_DEVICE_ID_ERROR "FPGA Device ID : Failed." /***********************/ /* I2C Test Error Code */ #define FPGA_I2C_GOOD 0x0000 #define FPGA_I2C_0_ERROR 0x0001 #define FPGA_I2C_1_ERROR 0x0002 #define FPGA_I2C_2_ERROR 0x0003 #define FPGA_PSOC_ERROR 0x0004 #define FPGA_I2C_HOT_SWAP_1_ERROR 0x0005 #define FPGA_I2C_HOT_SWAP_2_ERROR 0x0006 /* I2C Bus Test Description Message */ #define MSG_FPGA_I2C_GOOD "I2C Bus : Good." #define MSG_FPGA_I2C_0_ERROR "I2C Bus 0 : Failed." #define MSG_FPGA_I2C_1_ERROR "I2C Bus 1 : Failed." #define MSG_FPGA_I2C_2_ERROR "I2C Bus 2 : Failed." #define MSG_FPGA_PSOC_ERROR "PSOC Bus : Failed." #define MSG_FPGA_I2C_HOT_SWAP_1_ERROR "I2C Hot Swap 1 : Failed." #define MSG_FPGA_I2C_HOT_SWAP_2_ERROR "I2C Hot Swap 2 : Failed." /********************************************************* * QE8 *********************************************************/ #define MEC_QE8_DRIVE_C1 0x6BE0 #define MEC_QE8_DRIVE_C2 0x6BE1 #define MEC_QE8_HOST_C1 0x65D0 #define MEC_QE8_HOST_C2 0x65D1 #define MEC_QE8_HOST_C3 0x65D2 #define MEC_QE8_HOST_C4 0x65D3 /* ITEM */ #define QE8_ENABLE_PCI_DEV 0x01 // Enable PCI device fail #define QE8_INIT_CHIP 0x02 // initializa chip #define QE8_MEM_ALLOC 0x03 // Memory allocation #define QE8_GET_MEM 0x04 // Get memory requirement #define QE8_GET_IRQ 0x05 // Get IRQ #define QE8_CARD_NOT_FOUND 0x06 // QE8 card not found #define QE8_IPC_GET_RATE 0x07 // Failed to get the rate of remote SOC #define QE8_BS_CH_MISMATCH 0x08 // QE8 channel(s) mismatch #define QE8_DIAG_REGSET 0x11 // Diagnose register set #define QE8_DIAG_INT 0x12 // Diagnose interrupt #define QE8_DIAG_INTERLB 0x13 // Diagnose internal loopback #define QE8_DAIG_EX2INLB 0x14 // Diag external/internal loopback #define QE8_DIAG_EX2EXLB 0x15 // Diag external/external loopback #define QE8_DIAG_SGL_EX2INLB 0x16 // Diag SGL external/internal loopback #define QE8_DIAG_SGL_EX2EXLB 0x17 // Diag SGL external/external loopback #define QE8_DIAG_LOOPINIT 0x18 // Diag loop initialization /* ERROR CODE */ #define QE8_SUCCESS 0x0000 // success #define QE8_ENABLE_PCI_DEV_ERR 0x0011 // Enable PCI device fail #define QE8_INIT_CHIP_ERR 0x0012 // Init chip fail #define QE8_MEM_ALLOC_ERR 0x0013 // Memory allocation fail #define QE8_GET_MEM_ERR 0x0014 // Get memory requirement fail #define QE8_GET_IRQ_ERR 0x0015 // Get IRQ fail #define QE8_CARD_NOT_FOUND_ERR 0x0016 // QE8 card not found #define QE8_IPC_GET_RATE_ERR 0x0017 // Failed to get the rate of remote SOC #define QE8_BS_CH_MISMATCH_ERR 0x0018 // QE8 channel(s) mismatch #define QE8_DIAG_REGSET_ERR 0x0021 // Diagnose register set fail #define QE8_DIAG_INT_ERR 0x0022 // Diagnose interrupt fail #define QE8_DIAG_INTERLB_ERR 0x0023 // Diagnose internal loopback fail #define QE8_DIAG_EX2INLB_ERR 0x0024 // Diag external/internal loopback fail #define QE8_DIAG_EX2EXLB_ERR 0x0025 // Diag external/external loopback fail #define QE8_DIAG_SGL_EX2INLB_ERR 0x0026 // Diag SGL external/internal loopback fail #define QE8_DIAG_SGL_EX2EXLB_ERR 0x0027 // Diag SGL external/external loopback fail #define QE8_DIAG_LOOPINIT_ERR 0x0028 // Diag loop initialization fail /* Description Message */ #define QE8_ERR_MSG_SUCESS "Success" #define QE8_ERR_MSG_ENABLE_PCI "Failed to enable PCI Device" #define QE8_ERR_MSG_INIT_CHIP "Failed to initialize the QE8 chip" #define QE8_ERR_MSG_MEM_ALLOC "Failed to allocate memory" #define QE8_ERR_MSG_GET_MEM "Failed to get Memory Requirement" #define QE8_ERR_MSG_GET_IRQ "Failed to get an IRQ line" #define QE8_ERR_MSG_CARD_NOT_FOUND "QE8 card not found" #define QE8_ERR_MSG_IPC_GET_RATE "Failed to get the rate of remote SOC" #define QE8_ERR_MSG_BS_CH_MISMATCH "The available QE8 channels on the system are" /* Register diag description message */ #define QE8_DIAG_REGSET_GOOD "Diag QE8 register set: Good for channel" #define QE8_ERR_MSG_DIAG_REGSET "Failed to diag reigster set of QE8 for channel" /* Interrupt diag description message */ #define QE8_DIAG_INT_GOOD "Diag QE8 interrupt: Good for channel" #define QE8_ERR_MSG_DIAG_INT "Failed to diag interrupt of QE8 for channel" /* Internal loopback diag description message */ #define QE8_DIAG_INTERLB_GOOD "Diag internal loopback of QE8: Good for channel" #define QE8_ERR_MSG_DIAG_INTERLB "Failed to diag internal loopback of QE8 for channel" /* External/Internal loopback diag description message */ #define QE8_DIAG_EX2INLB_GOOD "Diag external TL/internal transceiver loopback of QE8: Good for channel" #define QE8_ERR_MSG_DIAG_EX2INLB "Failed to diag external TL/internal transceiver loopback of QE8 for channel" /* External/External loopback diag description message */ #define QE8_DIAG_EX2EXLB_GOOD "Diag external TL/external transceiver loopback of QE8: Good for channel" #define QE8_ERR_MSG_DIAG_EX2EXLB "Failed to diag external TL/external transceiver loopback of QE8 for channel" /* Scatter/Gatter list external/internal loopback diag description message */ #define QE8_DIAG_SGL_EX2INLB_GOOD "Diag scatter/gather external TL/internal tranceiver loopback of QE8: Good for channel" #define QE8_ERR_MSG_DIAG_SGL_EX2INLB "Failed to diag scatter/gather external TL/internal tranceiver loopback of QE8 for channel" /* External/External loopback diag description message */ #define QE8_DIAG_SGL_EX2EXLB_GOOD "Diag scatter/gather external TL/external transceiver loopback of QE8: Good for channel" #define QE8_ERR_MSG_DIAG_SGL_EX2EXLB "Failed to diag scatter/gather external TL/external transceiver loopback of QE8 for channel" /* Loop initialization diag description message */ #define QE8_DIAG_LOOPINIT_GOOD "Diag loop initialization of QE8: Good for channel" #define QE8_ERR_MSG_DIAG_LOOPINIT "Failed to diag loop initialization of QE8 for channel" /***********************/ /* LED Test Error Code */ #define FPGA_LED_GOOD 0x0000 #define FPGA_FRONT_LED_ERROR 0x0001 #define FPGA_ALT_RTR_LED_ERROR 0x0010 #define FPGA_SUMMARY_FAULT_LED_ERROR 0x0011 #define FPGA_TRAY_IDENTIFY_LED_ERROR 0x0012 #define FPGA_RTR_PS_0_LED_ERROR 0x0013 #define FPGA_RTR_PS_1_LED_ERROR 0x0014 #define FPGA_OVER_TEMP_LED_ERROR 0x0015 #define FPGA_DRIVE_LED_ERROR_BASE 0x0100 /* LED Test Description Message */ #define MSG_FPGA_LED_GOOD "LED Test : Good." #define MSG_FPGA_FRONT_LED_ERROR "Front Panel LED : Failed." #define MSG_FPGA_ALT_RTR_LED_ERROR "Alternate RTR LED : Failed." #define MSG_FPGA_SUMMARY_FAULT_LED_ERROR "Summary Fault LED : Failed." #define MSG_FPGA_TRAY_IDENTIFY_LED_ERROR "BOX ID LED : Failed." #define MSG_FPGA_RTR_PS_0_LED_ERROR "Power Supply 0 RTR LED : Failed." #define MSG_FPGA_RTR_PS_1_LED_ERROR "Power Supply 1 RTR LED : Failed." #define MSG_FPGA_OVER_TEMP_LED_ERROR "Over Temp LED : Failed." #define MSG_FPGA_DRIVE_LED_ERROR "Drive LED : Failed." /****************************/ /* EPP Interface Error Code */ //EPP Interface #define FPGA_EPP_GOOD 0x0000 #define FPGA_EPP_ERROR 0x0001 /* EPP Interface Test Description Message */ #define MSG_FPGA_EPP_GOOD "EPP Interface : Good." #define MSG_FPGA_EPP_ERROR "EPP Interface : Failed." /*******************************/ /* NVSRAM Lock Test Error Code */ #define FPGA_NVSRAM_LOCK_GOOD 0x0000 #define FPGA_NVSRAM_LOCK_ERROR_BASE 0x0100 /* NVSRAM Lock Test Description Message */ #define MSG_FPGA_NVSRAM_LOCK_GOOD "NVSRAM Lock : Good." #define MSG_FPGA_NVSRAM_LOCK_ERROR "NVSRAM Lock : Failed." /*********************************/ /* Drive Inplace Test Error Code */ #define FPGA_DRIVE_INPLACE_GOOD 0x0000 #define FPGA_DRIVE_INPLACE_ERROR_BASE 0x0100 /* Drive Inplace Test Description Message */ #define MSG_FPGA_DRIVE_INPLACE_GOOD "Drive Inplace : Good." #define MSG_FPGA_DRIVE_INPLACE_ERROR "Drive Inplace : Failed." /***********************************/ /* Protected Write Test Error Code */ #define FPGA_PROTECTED_WRITE_GOOD 0x0000 #define FPGA_PROTECTED_WRITE_1_ERROR 0x0001 #define FPGA_PROTECTED_WRITE_2_ERROR 0x0002 #define FPGA_PROTECTED_WRITE_3_ERROR 0x0003 #define FPGA_PROTECTED_WRITE_4_ERROR 0x0004 /* Protected Write Test Description Message */ #define MSG_FPGA_PROTECTED_WRITE_GOOD "Protected Write Test : Good." #define MSG_FPGA_PROTECTED_WRITE_1_ERROR "Protected Write 1 : Failed." #define MSG_FPGA_PROTECTED_WRITE_2_ERROR "Protected Write 2 : Failed." #define MSG_FPGA_PROTECTED_WRITE_3_ERROR "Protected Write 3 : Failed." #define MSG_FPGA_PROTECTED_WRITE_4_ERROR "Protected Write 4 : Failed." /*************************************/ /* Program Interface Test Error Code */ #define FPGA_PROGRAM_GOOD 0x0000 #define FPGA_PROGRAM_ERROR 0x0003 #define FPGA_EPCS_ERROR 0x0001 #define FPGA_PROGRAM_INTERFACE_ERROR 0x0002 /* Program Interface Test Description Message */ #define MSG_FPGA_PROGRAM_GOOD "FPGA Program Interface : Good." #define MSG_FPGA_PROGRAM_ERROR "FPGA Program Interface : Failed." #define MSG_FPGA_EPCS_ERROR "FPGA EPCS : Failed." #define MSG_FPGA_PROGRAM_INTERFACE_ERROR "FPGA Program Interface : Failed." /*************************/ /* Reset Test Error Code */ #define FPGA_RESET_GOOD 0x0000 #define FPGA_ALT_RST_IN_ERROR 0x0010 #define FPGA_ALT_RST_OUT_ERROR 0x0011 #define FPGA_ALT_RST_CLEAR_ERROR 0x0012 #define FPGA_BOARD_RESET_ERROR 0x0030 #define FPGA_ETHERNET_RESET_ERROR 0x0032 #define FPGA_PCIE_SWITCH_RESET_ERROR 0x0033 #define FPGA_I2C_MUX_RESET_ERROR 0x0034 #define FPGA_PSOC_RESET_ERROR 0x0043 #define FPGA_I2C_MDPL1_RESET_ERROR 0x0044 #define FPGA_I2C_MDPL2_RESET_ERROR 0x0045 #define FPGA_CPLD_RESET_ERROR 0x0046 #define FPGA_ISATA_RESET_ERROR 0x0047 #define FPGA_SAS2IOC_RESET_ERROR 0x0048 #define FPGA_SAS2X36_RESET_ERROR 0x0049 #define FPGA_QE8_RESET_ERROR 0x004A #define FPGA_QE8_4TO1_ERROR 0x004B #define FPGA_DIRECTED_RESET_ERROR 0x0050 #define FPGA_DIRECTED_RESET_CLEAR_ERROR 0x0051 #define FPGA_DIRECTED_RESET_MASK_ERROR 0x0052 /* Reset Test Description Message */ #define MSG_FPGA_RESET_GOOD "Reset Test : Good." #define MSG_FPGA_ALT_RST_IN_ERROR "Alternate Reset In : Failed." #define MSG_FPGA_ALT_RST_OUT_ERROR "Alternate Reset Out : Failed." #define MSG_FPGA_ALT_RST_CLEAR_ERROR "Alternate Reset Clear : Failed." #define MSG_FPGA_BOARD_RESET_ERROR "PCI Reset : Failed." #define MSG_FPGA_ETHERNET_RESET_ERROR "Ethernet Reset : Failed." #define MSG_FPGA_PCIE_SWITCH_RESET_ERROR "PCIE Switch : Failed." #define MSG_FPGA_I2C_MUX_RESET_ERROR "I2C MUX Reset : Failed." #define MSG_FPGA_PSOC_RESET_ERROR "PSOC Reset : Failed." #define MSG_FPGA_I2C_MDPL1_RESET_ERROR "Midplane I2C 1 Reset : Failed." #define MSG_FPGA_I2C_MDPL2_RESET_ERROR "Midplane I2C 2 Reset : Failed." #define MSG_FPGA_CPLD_RESET_ERROR "CPLD Reset : Failed." #define MSG_FPGA_ISATA_RESET_ERROR "iSATA Reset : Failed." #define MSG_FPGA_SAS2IOC_RESET_ERROR "LSI SAS2008 Falcon Reset : Failed." #define MSG_FPGA_SAS2X36_RESET_ERROR "LSI SAS2X36 Bobcat Reset : Failed." #define MSG_FPGA_QE8_RESET_ERROR "QE8 Reset : Failed." #define MSG_FPGA_QE8_4TO1_ERROR "QE8 4-function to 1-function : Failed." #define MSG_FPGA_DIRECTED_RESET_ERROR "Directed Reset : Failed." #define MSG_FPGA_DIRECTED_RESET_CLEAR_ERROR "Clear Directed Reset : Failed." #define MSG_FPGA_DIRECTED_RESET_MASK_ERROR "Directed Reset Mask : Failed." /***********************/ /* CWT Test Error Code */ #define FPGA_CWT_GOOD 0x0000 #define FPGA_CWT_WARNING_ERROR 0x0001 #define FPGA_CWT_FAULTED_ERROR 0x0002 #define FPGA_CWT_RESET_ERROR 0x0003 #define FPGA_CWT_TIMER_ERROR 0x0004 /* CWT Test Description Message */ #define MSG_FPGA_CWT_GOOD "CWT Test : Good." #define MSG_FPGA_CWT_WARNING_ERROR "CWT Warning State : Failed." #define MSG_FPGA_CWT_FAULTED_ERROR "CWT Faulted State : Failed." #define MSG_FPGA_CWT_RESET_ERROR "CWT Reset : Failed." #define MSG_FPGA_CWT_TIMER_ERROR "CWT Timer : Failed. Too soon to reset!!" /*****************************/ /* Interrupt Test Error Code */ #define FPGA_INTERRUPT_MASK_GOOD 0x0000 #define FPGA_SUBSYSTEM_INT_ERROR 0x0001 #define FPGA_SUBSYSTEM_INT_MASK_ERROR 0x0002 #define FPGA_CLEAR_SUBSYSTEM_INT_ERROR 0x0003 #define FPGA_INT_MASK_ERROR_BASE 0x0011 #define FPGA_NMI_ERROR 0x0031 #define FPGA_ALTERNATE_NMI_OUT_ERROR 0x0040 #define FPGA_ALTERNATE_NMI_IN_ERROR 0x0041 #define FPGA_CLEAR_ALTERNATE_NMI_IN_ERROR 0x0042 #define FPGA_PUSH_BTN_ERROR 0x0050 #define FPGA_CLEAR_PUSH_BTN_ERROR 0x0051 /* Interrupt Test Description Message */ #define MSG_FPGA_INTERRUPT_MASK_GOOD "Interrupt & Mask Test : Good." #define MSG_FPGA_SUBSYSTEM_INT_ERROR "Subsystem INT : Failed." #define MSG_FPGA_SUBSYSTEM_INT_MASK_ERROR "Subsystem INT Mask : Failed." #define MSG_FPGA_CLEAR_SUBSYSTEM_INT_ERROR "Clear Subsystem INT Latch : Failed." #define MSG_FPGA_NMI_ERROR "FPGA NMI to Processor : Failed." #define MSG_FPGA_ALTERNATE_NMI_OUT_ERROR "Alternate NMI Out Pin : Failed." #define MSG_FPGA_ALTERNATE_NMI_IN_ERROR "Alternate NMI In Pin : Failed." #define MSG_FPGA_CLEAR_ALTERNATE_NMI_IN_ERROR "Clear Alternate NMI In Latch : Failed." #define MSG_FPGA_INT_MASK_ERROR_BASE "INT Mask : Failed." /******************************************************************** INT_MASK_ERROR_MASSAGE[1,i] {'', 'PS_AC_GOOD_INT_MASK_ERROR', '', '', '', '', '', '' } INT_MASK_ERROR_MASSAGE[2,i] 'PS0_FAULT_MASK_ERROR', 'PS1_FAULT_MASK_ERROR', 'CPU_TEMP_INT_MASK_ERROR', 'TMP_MASK_ERROR', '', 'ALARM_CANCEL_MASK_ERROR', 'PS0_OVER_TEMP_MASK_ERROR', 'PS1_OVER_TEMP_MASK_ERROR' } INT_MASK_ERROR_MASSAGE[3,i] 'PS0_INPL_MASK_ERROR', 'PS1_INPL_MASK_ERROR', 'BBU_INPL_MASK_ERROR', 'ALT_INPL_MASK_ERROR', '', 'BBU_ENABLE_MASK_ERROR', '', '' } *********************************************************************/ #define MSG_FPGA_PUSH_BTN_ERROR "Push Button: Failed." #define MSG_FPGA_CLEAR_PUSH_BTN_ERROR "Clear Push Button Latch: Failed." /****************************/ /* BBU & PS Test Error Code */ //BBU part #define FPGA_BBU_GOOD 0x0000 #define FPGA_BBU_INPLACE_ERROR 0x0001 #define FPGA_BBU_DISABLE_ERROR 0x0002 #define FPGA_BBU_ENABLE_ERROR 0x0003 #define FPGA_BBU_MONITOR_ERROR 0x0004 #define FPGA_BBU_DRAWING_ERROR 0x0005 #define FPGA_BBU_DISCHARGE_ERROR 0x0006 #define FPGA_BBU_PIN_ERROR 0x0007 #define FPGA_BBU_VCC12_ERROR 0x0008 #define FPGA_BBU_POWER_SWITCH_ERROR 0x0009 //Power supply part #define FPGA_PS_GOOD 0x0010 #define FPGA_PS_MAIN_PWR_FAIL_ERROR 0x0011 #define FPGA_PS_PWR_FAIL_LATCH_ERROR 0x0012 #define FPGA_PS_CLEAR_PWR_FAIL_LATCH_ERROR 0x0013 #define FPGA_PS_AC_GOOD_ERROR 0x0014 #define FPGA_PS_0_FAULT_ERROR 0x0015 #define FPGA_PS_1_FAULT_ERROR 0x0016 #define FPGA_PS_0_INPLACE_ERROR 0x0017 #define FPGA_PS_1_INPLACE_ERROR 0x0018 #define FPGA_PS0_OVER_TEMP_ERROR 0x0019 #define FPGA_PS1_OVER_TEMP_ERROR 0x001A #define FPGA_PS_CONTROL_ERROR 0x001B #define FPGA_PS_CLEAR_MAIN_PWR_FAIL_LATCH_ERROR 0x001C #define FPGA_PS_MAIN_PWR_FAIL_LATCH_ERROR 0x001D #define FPGA_PS_HOST_CARD_DISABLE_ERROR 0x0020 #define FPGA_HOST_CARD_RESET_ERROR 0x0021 /* BBU & PS Test Description Message */ //BBU part #define MSG_FPGA_BBU_GOOD "BBU Test : Good." #define MSG_FPGA_BBU_INPLACE_ERROR "BBU Inplace : Failed." #define MSG_FPGA_BBU_DISABLE_ERROR "BBU Disable : Failed." #define MSG_FPGA_BBU_ENABLE_ERROR "BBU Enable : Failed." #define MSG_FPGA_BBU_MONITOR_ERROR "BBU Monitor : Failed." #define MSG_FPGA_BBU_DRAWING_ERROR "BBU BKUP_FET_ON_L : Failed." #define MSG_FPGA_BBU_DISCHARGE_ERROR "BBU Discharge : Failed." #define MSG_FPGA_BBU_PIN_ERROR "BBU BATT PIN: Failed." #define MSG_FPGA_BBU_VCC12_ERROR "BBU VCC12 PIN: Failed." #define MSG_FPGA_BBU_POWER_SWITCH_ERROR "Switch Power From BBU to PS: Failed." //Power supply part #define MSG_FPGA_PS_GOOD "Power Supply Test : Good." #define MSG_FPGA_PS_MAIN_PWR_FAIL_ERROR "Main Power Fail : Failed." #define MSG_FPGA_PS_PWR_FAIL_LATCH_ERROR "Power Fail Latch : Failed." #define MSG_FPGA_PS_CLEAR_PWR_FAIL_LATCH_ERROR "Clear Power Fail Latch : Failed." #define MSG_FPGA_PS_AC_GOOD_ERROR "Power Supply AC Good : Failed." #define MSG_FPGA_PS_0_FAULT_ERROR "Power Supply 0 Fault : Failed." #define MSG_FPGA_PS_1_FAULT_ERROR "Power Supply 1 Fault : Failed." #define MSG_FPGA_PS_0_INPLACE_ERROR "Power Supply 0 Inplace : Failed." #define MSG_FPGA_PS_1_INPLACE_ERROR "Power Supply 1 Inplace : Failed." #define MSG_FPGA_PS0_OVER_TEMP_ERROR "PS0 Over Temp Pin : Failed." #define MSG_FPGA_PS1_OVER_TEMP_ERROR "PS1 Over Temp Pin : Failed." #define MSG_FPGA_PS_CONTROL_ERROR "PS Control Pin : Failed." #define MSG_FPGA_PS_CLEAR_MAIN_PWR_FAIL_LATCH_ERROR "Clear Main Power Fail Latch : Failed." #define MSG_FPGA_PS_MAIN_PWR_FAIL_LATCH_ERROR "Main Power Fail Latch : Failed." #define MSG_FPGA_HOST_CARD_RESET_ERROR "Host Card Reset : Failed." #define MSG_FPGA_PS_HOST_CARD_DISABLE_ERROR "Host Card Power Disable : Failed." /*********************************/ /* Miscellaneous Test Error Code */ //alarm #define FPGA_MISCELLANEOUS_GOOD 0x0000 #define FPGA_ALARM_ERROR 0x0001 #define FPGA_ALARM_CANCEL_INT_ERROR 0x0002 #define FPGA_CLEAR_ALARM_CANCEL_INT_ERROR 0x0003 #define MSG_FPGA_MISCELLANEOUS_GOOD "Miscellaneous Pin Test : Good." #define MSG_FPGA_ALARM_ERROR "Audio Alarm : Failed." #define MSG_FPGA_ALARM_CANCEL_INT_ERROR "Audio Alarm Cancel INT : Failed." #define MSG_FPGA_CLEAR_ALARM_CANCEL_INT_ERROR "Clear Audio Alarm Cancel INT : Failed." //fireware running #define FPGA_FW_RUNNING_ERROR 0x0004 #define FPGA_ALT_FW_RUNNING_ERROR 0x0005 #define MSG_FPGA_FW_RUNNING_ERROR "Firmware Running Pin : Failed." #define MSG_FPGA_ALT_FW_RUNNING_ERROR "Alternate Firmware Running Pin : Failed." //cross board #define FPGA_SS_ID_ERROR 0x0010 #define FPGA_CONT_POSN_ERROR 0x0011 #define FPGA_HARNESS_INPL_ERROR 0x0012 #define FPGA_ALT_INPL_IN_ERROR 0x0013 #define FPGA_CLEAR_ALT_INPL_IN_ERROR 0x0014 #define FPGA_ALT_RAID_ESM_ERROR 0x0021 #define MSG_FPGA_SS_ID_ERROR "Subsystem ID Pins : Failed." #define MSG_FPGA_CONT_POSN_ERROR "Controller Position Pin : Failed." #define MSG_FPGA_HARNESS_INPL_ERROR "Harness Inplace Pin : Failed." #define MSG_FPGA_ALT_INPL_IN_ERROR "Alternate Controller Inplace Pin : Failed." #define MSG_FPGA_CLEAR_ALT_INPL_IN_ERROR "Clear Alternate Controller Inplace INT : Failed." #define MSG_FPGA_ALT_RAID_ESM_ERROR "Alternate RAID/ESM Pin : Failed." //switch buffer #define FPGA_EN_PAIRING_ERROR 0x0030 #define FPGA_EN_LS_INTER_CON_ERROR 0x0031 #define FPGA_EN_LS_CROSS_L_ERROR 0x0032 #define MSG_FPGA_EN_PAIRING_ERROR "EN_LS_PAIRING Pin : Failed." #define MSG_FPGA_EN_LS_INTER_CON_ERROR "EN_LS_INTER_CON Pin : Failed." #define MSG_FPGA_EN_LS_CROSS_L_ERROR "EN_LS_CROSS_L Pin : Failed." #if 0 //FPGA /* Midplane LED Test Error Code */ #define FPGA_RDY_RMV_LED_GOOD 0x0000 #define FPGA_RDY_RMV_LED_ERROR 0x0001 /* Midplane I2C Test Error Code */ #define FPGA_MIDPLANE_I2C_GOOD 0x0000 #define FPGA_EXT_SCL1_ERROR 0x0001 #define FPGA_EXT_SDA1_ERROR 0x0002 #define FPGA_EXT_SCL2_ERROR 0x0003 #define FPGA_EXT_SDA2_ERROR 0x0004 #define FPGA_SCL_I2C_GLOBAL_ERROR 0x0005 #define FPGA_SDA_I2C_GLOBAL_ERROR 0x0006 /* Midplane Miscellaneous Pin Test Error Code */ #define FPGA_MIDPLANE_MIS_GOOD 0x0000 #define FPGA_INPL_L_ERROR 0x0001 #define FPGA_RAID_ESM_L_ERROR 0x0002 #define FPGA_COMBINED_ID_0_ERROR 0x0003 #define FPGA_COMBINED_ID_1_ERROR 0x0004 #define FPGA_COMBINED_ID_2_ERROR 0x0005 #define FPGA_COMBINED_ID_3_ERROR 0x0006 #define FPGA_MIDPLANE_DRIVE_INPL_ERROR 0x0010 #define FPGA_MIDPLANE_DRIVE_FAULT_ERROR 0x0011 #define FPGA_MIDPLANE_DRIVE_BYPASS_ERROR 0x0012 #define FPGA_MIDPLANE_9545_ERROR 0x0020 #define FPGA_MIDPLANE_9555_ERROR 0x0021 #define FPGA_MIDPLANE_INA209_ERROR 0x0022 /* Miscellaneous Test Description Message */ #define MSG_FPGA_TEST_MODE_ERROR "Test Mode : Failed." #define MSG_FPGA_CARD_IO_TEST_ERROR "Card IO Test Pin : Failed." //Mattahorn only #define MSG_FPGA_ALT_BD_ID_ERROR "Alternate Board ID Pins : Failed." #define MSG_FPGA_CORTINA_MIDPLANE_ERROR "Cortina Midplane Pin : Failed." #define MSG_FPGA_PS0_OVER_TEMP_ERROR "Power Supply 0 Over Temp Pin : Failed." #define MSG_FPGA_PS1_OVER_TEMP_ERROR "Power Supply 1 Over Temp Pin : Failed." //Chamonix only #define MSG_FPGA_MP0_OVER_TEMP_ERROR "Midplane Over Temp Pin : Failed." /* Midplane LED Test Description Message */ #define MSG_FPGA_RDY_RMV_LED_GOOD "RDY_RMV_LED_IN Pin : Good." #define MSG_FPGA_RDY_RMV_LED_ERROR "RDY_RMV_LED_IN Pin : Failed." /* Midplane I2C Test Description Message */ #define MSG_FPGA_MIDPLANE_I2C_GOOD "Midplane I2C Connection : Good." #define MSG_FPGA_EXT_SCL1_ERROR "Midplane EXT_SCL1 Pin : Failed." #define MSG_FPGA_EXT_SDA1_ERROR "Midplane EXT_SDA1 Pin : Failed." #define MSG_FPGA_EXT_SCL2_ERROR "Midplane EXT_SCL2 Pin : Failed." #define MSG_FPGA_EXT_SDA2_ERROR "Midplane EXT_SDA2 Pin : Failed." #define MSG_FPGA_SCL_I2C_GLOBAL_ERROR "Midplane SCL_I2C_GLOBAL Pin : Failed." #define MSG_FPGA_SDA_I2C_GLOBAL_ERROR "Midplane SDA_I2C_GLOBAL Pin : Failed." /* Midplane Miscellaneous Pin Test Description Message */ #define MSG_FPGA_MIDPLANE_MIS_GOOD "Midplane Miscellaneous Pins : Good." #define MSG_FPGA_INPL_L_ERROR "INPL_L Pin : Failed." #define MSG_FPGA_RAID_ESM_L_ERROR "RAID_ESM_L Pin : Failed." #define MSG_FPGA_COMBINED_ID_0_ERROR "COMBINED_ID_0 Pin : Failed." #define MSG_FPGA_COMBINED_ID_1_ERROR "COMBINED_ID_1 Pin : Failed." #define MSG_FPGA_COMBINED_ID_2_ERROR "COMBINED_ID_2 Pin : Failed." #define MSG_FPGA_COMBINED_ID_3_ERROR "COMBINED_ID_3 Pin : Failed." #define MSG_FPGA_MIDPLANE_DRIVE_INPL_ERROR "Midplane Drive INPL Pin : Failed." #define MSG_FPGA_MIDPLANE_DRIVE_FAULT_ERROR "Midplane Drive FAULT Pin : Failed." #define MSG_FPGA_MIDPLANE_DRIVE_BYPASS_ERROR "Midplane Drive BYPASS Pin : Failed." #define MSG_FPGA_MIDPLANE_9545_ERROR "Midplane 9545 Transfer: Failed." #define MSG_FPGA_MIDPLANE_9555_ERROR "Midplane 9555 Transfer: Failed." #define MSG_FPGA_MIDPLANE_INA209_ERROR "Midplane INA209 Transfer: Failed." #endif //FPGA /********************************************************* * * PCH USB host controller **********************************************************/ /* Item */ #define USB_DIAG_ITEM_CODE_INTERFACE 0x01 #define USB_DIAG_ITEM_CODE_TRANSFER 0x02 #define USB_DIAG_ITEM_CODE_PERFORMANCE 0x03 /* Error code*/ #define USB_DIAG_ERROR_CODE_KMALLOC_FAILED 0x01 #define USB_DIAG_ERROR_CODE_RD_CMD_EXEC_FAILED 0x02 #define USB_DIAG_ERROR_CODE_WR_CMD_EXEC_FAILED 0x03 #define USB_DIAG_ERROR_CODE_USB_CONFIG_ERR 0x04 #define USB_DIAG_ERROR_CODE_SECTOR_SIZE_ERR 0x05 #define USB_DIAG_ERROR_CODE_TOTAL_SECTOR_ERR 0x06 #define USB_DIAG_ERROR_CODE_DATA_TRANSFER_ERR 0x07 #define USB_DIAG_ERROR_CODE_PERFORMANCE_FAILED 0x07 #define USB_DIAG_ERROR_CODE_DEVICE_DETECT_FAILED 0x09 #define USB_DIAG_ERROR_CODE_CAPACITY_ERROR 0x0A /* Description Message */ #define USB_DIAG_ERROR_MSG_KMALLOC_FAILED "Kernel resource allocate failed" #define USB_DIAG_ERROR_MSG_RD_CMD_EXEC_FAILED "USB read command execute failed" #define USB_DIAG_ERROR_MSG_WR_CMD_EXEC_FAILED "USB write command execute failed" #define USB_DIAG_ERROR_MSG_USB_CONFIG_ERR "USB configuration error" #define USB_DIAG_ERROR_MSG_SECTOR_SIZE_ERR "Read incorrect sector size" #define USB_DIAG_ERROR_MSG_TOTAL_SECTOR_ERR "Read incorrect total sector" #define USB_DIAG_ERROR_MSG_DATA_TRANSFER_ERR "Data transfer error" #define USB_DIAG_ERROR_MSG_PERFORMANCE_FAILED "Performance test faild" #define USB_DIAG_ERROR_MSG_DEVICE_DETECT_FAILED "Flash device detection failed" #define USB_DIAG_ERROR_MSG_CAPACITY_ERROR "Flash device read last sector error" /********************************************************* * * PCH SATA host controller **********************************************************/ /* Item */ #define SATA_DIAG_ITEM_CODE_P0_INTERFACE 0x01 #define SATA_DIAG_ITEM_CODE_P1_INTERFACE 0x02 #define SATA_DIAG_ITEM_CODE_P0_TRANSFER 0x03 #define SATA_DIAG_ITEM_CODE_P1_TRANSFER 0x04 #define SATA_DIAG_ITEM_CODE_P0_RAND_WRITE_VERIFY 0x05 #define SATA_DIAG_ITEM_CODE_P1_RAND_WRITE_VERIFY 0x06 #define SATA_DIAG_ITEM_CODE_P0_PERFORMANCE 0x07 #define SATA_DIAG_ITEM_CODE_P1_PERFORMANCE 0x08 /* Error code*/ #define SATA_DIAG_ERROR_CODE_KMALLOC_FAILED 0x01 #define SATA_DIAG_ERROR_CODE_RD_CMD_EXEC_FAILED 0x02 #define SATA_DIAG_ERROR_CODE_WR_CMD_EXEC_FAILED 0x03 #define SATA_DIAG_ERROR_CODE_DATA_TRANSFER_ERR 0x04 #define SATA_DIAG_ERROR_CODE_RAND_WRITE_VERIFY_ERR 0x05 #define SATA_DIAG_ERROR_CODE_PERFORMANCE_FAILED 0x06 #define SATA_DIAG_ERROR_CODE_DEVICE_DETECT_FAILED 0x07 #define SATA_DIAG_ERROR_CODE_PORT_DETECT_FAILED 0x08 #define SATA_DIAG_ERROR_CODE_HOST_DETECT_FAILED 0x09 #define SATA_DIAG_ERROR_CODE_CAPACITY_ERROR 0x0A /* Description Message */ #define SATA_DIAG_ERROR_MSG_KMALLOC_FAILED "Kernel resource allocate failed" #define SATA_DIAG_ERROR_MSG_RD_CMD_EXEC_FAILED "SATA read command execute failed" #define SATA_DIAG_ERROR_MSG_WR_CMD_EXEC_FAILED "SATA write command execute failed" #define SATA_DIAG_ERROR_MSG_DATA_TRANSFER_ERR "Data transfer error" #define SATA_DIAG_ERROR_MSG_RAND_WRITE_VERIFY_ERR "Rand Write Verity Test error" #define SATA_DIAG_ERROR_MSG_RAND_WRITE_VERIFY_TIMEOUT "Rand Write Verity Test timeout" #define SATA_DIAG_ERROR_MSG_PERFORMANCE_FAILED "Performance test faild" #define SATA_DIAG_ERROR_MSG_DEVICE_DETECT_FAILED "SATA devices detection failed" #define SATA_DIAG_ERROR_MSG_PORT_DETECT_FAILED "Host controller port detection failed" #define SATA_DIAG_ERROR_MSG_HOST_DETECT_FAILED "Host controller detection failed" #define SATA_DIAG_ERROR_MSG_CAPACITY_ERROR "SATA device read last sector error" /********************************************************* * Ibex Peak PCH **********************************************************/ /* Item */ #define PATSBURG_PROCESSOR_INTERFACE_MEC 0x01 #define PATSBURG_PCIE_MEC 0x02 #define PATSBURG_PCI_MEC 0x03 #define PATSBURG_SMBUS_MEC 0x04 #define PATSBURG_POWER_MANAGEMENT_MEC 0x05 #define PATSBURG_INTERRUPT_GPIO_MEC 0x06 #define PATSBURG_RTC_MEC 0x07 #define PATSBURG_LPC_MEC 0x08 /* Error code*/ #define PROCESSOR_INTERFACE_ERROR 0x0101 #define SATA_D3_MODE_ERROR 0x0501 #define USB_D3_MODE_ERROR 0x0502 #define PCIE_D3_MODE_ERROR 0x0503 #define NIC82579_D3_MODE_ERROR 0x0504 #define PATSBURG_PCI_NO_DEVICE_ERROR 0x0201 #define PATSBURG_PCI_REG_READ_ERROR 0x0202 #define PATSBURG_PCI_ADDR_LINE_ERROR 0x0203 #define PATSBURG_PCI_DATA_LINE_ERROR 0x0204 #define PATSBURG_PCI_WRONG_LANE_ERROR 0x0205 #define GPIO_BOARD_ID_SKU0_ERROR 0x0601 #define GPIO_BOARD_ID_SKU1_ERROR 0x0602 #define GPIO_BOARD_ID_SKU2_ERROR 0x0603 #define GPIO_BOARD_ID_SKU3_ERROR 0x0604 /* message */ #define MSG_PROCESSOR_INTERFACE_ERROR "Processor interface test: Failed." #define MSG_SATA_D3_MODE_ERROR "SATA D3 mode test: Failed." #define MSG_USB_D3_MODE_ERROR "USB D3 mode test: Failed." #define MSG_PCIE_D3_MODE_ERROR "PCI-E port D3 mode test: Failed." #define MSG_NIC82579_D3_MODE_ERROR "NIC82579 D3 mode test: Failed." #define MSG_PATSBURG_PCI_NO_DEVICE_ERROR "PCI device is not detected." #define MSG_PATSBURG_PCI_REG_READ_ERROR "PCI register read test: Failed." #define MSG_PATSBURG_PCI_ADDR_LINE_ERROR "PCI address lines test: Failed." #define MSG_PATSBURG_PCI_DATA_LINE_ERROR "PCI data lines test: Failed." #define MSG_PATSBURG_PCI_WRONG_LANE_ERROR "PCI-E link width: Not correct." #define MSG_GPIO_BOARD_ID_SKU0_ERROR "GPIO-Board ID SKU0 test: Failed." #define MSG_GPIO_BOARD_ID_SKU1_ERROR "GPIO-Board ID SKU1 test: Failed." #define MSG_GPIO_BOARD_ID_SKU2_ERROR "GPIO-Board ID SKU2 test: Failed." #define MSG_GPIO_BOARD_ID_SKU3_ERROR "GPIO-Board ID SKU3 test: Failed." /********************************************************* * RTC **********************************************************/ /* ITEM */ #define RTC_ITEM_1 1 #define RTC_ITEM_2 2 /* ERROR CODE */ #define RTC_CODE_1 1 #define RTC_CODE_2 2 #define RTC_CODE_3 3 #define RTC_CODE_4 4 /* Description Message */ #define RTC_ERR_MSG_1 "Real Time Clock not tick" #define RTC_ERR_MSG_2 "RTC failed to increment" #define RTC_ERR_MSG_3 "RTC failed to increment by 4 after 4.925 sec." #define RTC_ERR_MSG_4 "RTC failed to increment by 5 after 5.075 sec." /********************************************************* * I2C/SMBUS **********************************************************/ /* Item */ #define I2C_DG_ITEM_INIT 0 #define I2C_DG_ITEM_PCH_MASTER 1 #define I2C_DG_ITEM_PCH_BUS_LINE 2 #define I2C_DG_ITEM_ZEBULON_BUS_LINE 3 #define I2C_DG_ITEM_PCA9548 4 #define I2C_DG_ITEM_PCA9548_CHANN 5 #define I2C_DG_ITEM_SAS2008_EEPROM 6 #define I2C_DG_ITEM_VPD_EEPROM 7 /* Error code */ #define I2C_DG_CODE_INIT 0x0000 #define I2C_DG_CODE_PCH_REG 0x0001 #define I2C_DG_CODE_PCH_SDA 0x0002 #define I2C_DG_CODE_PCH_SCL 0x0003 #define I2C_DG_CODE_PCH_BUS_LINE 0x0004 #define I2C_DG_CODE_ZEBULON_BUS_LINE 0x0005 #define I2C_DG_CODE_PCA9548 0x0006 #define I2C_DG_CODE_PCA9548_CHANN 0x0007 #define I2C_DG_CODE_SAS2008_EEPROM 0x0008 #define I2C_DG_CODE_VPD_EEPROM 0x0009 /* Description Message */ #define I2C_DG_MSG_PCH_INIT_FAILED "I2C PCH controller initialization failed" #define I2C_DG_MSG_PCH_REG "I2C PCH controller register test failed" #define I2C_DG_MSG_PCH_SDA "I2C PCH controller sda line test failed" #define I2C_DG_MSG_PCH_SCL "I2C PCH controller scl line test failed" #define I2C_DG_MSG_PCH_BUS_LINE "I2C PCH controller bus line test failed" #define I2C_DG_MSG_ZEBULON_BUS_LINE "I2C FPGA Zebulon controller bus line test failed" #define I2C_DG_MSG_PCA9548_READ "I2C Read Pca9548 register failed" #define I2C_DG_MSG_PCA9548_WRITE "I2C Write Pca9548 register failed" #define I2C_DG_MSG_PCA9548_REG "I2C Switching Pca9548 channel failed" #define I2C_DG_MSG_PCA9548_RESET "I2C Pca9548 reset line test failed" #define I2C_DG_MSG_PCA9548_CHANN "I2C Pca9548 channel line test failed" #define I2C_DG_MSG_SAS2008_EEPROM "I2C SAS2008 EEPROM test failed" #define I2C_DG_MSG_VPD_EEPROM "I2C VPD EEPROM test failed" #define I2C_DG_MSG_ICT_MB_VPD_EEPROM "I2C ICT Main Board VPD EEPROM Verification Test failed" #define I2C_DG_MSG_ICT_HIC_VPD_EEPROM "I2C ICT Host Card VPD EEPROM Verification Test failed" /********************************************************* * Temperature sensor (max6657) *********************************************************/ /* ITEM */ #define TEMP_SENSOR_ITEM_SENSOR 1 #define TEMP_SENSOR_ITEM_ALERT 2 #define TEMP_SENSOR_ITEM_OVERT 3 /* ERROR CODE */ #define TEMP_SENSOR_CODE_SENSOR 1 #define TEMP_SENSOR_CODE_ALERT 2 #define TEMP_SENSOR_CODE_OVERT 3 /* Description Message */ #define TEMP_SENSOR_MSG_EIO "Temp Sensor: access device failed" #define TEMP_SENSOR_MSG_EPEER "Temp Sensor: failed to get temperature of peer controller" #define TEMP_SENSOR_MSG_EVALUE "Temp Sensor: measured unreasonable temperature value" #define TEMP_SENSOR_MSG_EALERT_ASSERT "Temp Sensor: FPGA did not detect ALERT assert" #define TEMP_SENSOR_MSG_EALERT_DEASSERT "Temp Sensor: FPGA did not detect ALERT deassert" /********************************************************* * PCI-E Switch *********************************************************/ /* Item */ #define PCIE_SWITCH_ITEM_CFG 1 #define PCIE_SWITCH_ITEM_NTB 2 /* Error code*/ #define PCIE_SWITCH_CODE_CFG 0x0001 #define PCIE_SWITCH_CODE_NTB 0x0002 /* Description Message */ #define PCIE_SWITCH_MSG_ESCAN "PCI-E switch not found" #define PCIE_SWITCH_MSG_EPORTS "PCI-E switch port configuration error" #define PCIE_SWITCH_MSG_ESTATUS "PCI-E switch detected port pci status error" #define PCIE_SWITCH_MSG_EWIDTH "PCI-E switch detected port with wrong lane width" #define PCIE_SWITCH_MSG_NTB_EINIT "PCI-E switch failed to initialize NT bridge" #define PCIE_SWITCH_MSG_NTB_ETIMEDOUT "PCI-E switch NTB request timeout" #define PCIE_SWITCH_MSG_NTB_EADDRLINE "PCI-E switch NTB address line test failed" #define PCIE_SWITCH_MSG_NTB_EDATALINE "PCI-E switch NTB data line test failed" /********************************************************* * Intel 82576 Ethernet Controller *********************************************************/ /* Item */ #define NIC82576_ITEM_MDI 1 #define NIC82576_ITEM_LINK 2 #define NIC82576_ITEM_REG 3 #define NIC82576_ITEM_EEPROM 4 #define NIC82576_ITEM_INTR 5 #define NIC82576_ITEM_LOOPBACK 6 #define NIC82576_ITEM_CLOOPBACK 7 #define NIC82576_ITEM_STRESS 8 /* Error Code */ #define NIC82576_CODE_MDI 1 #define NIC82576_CODE_LINK 2 #define NIC82576_CODE_REG 3 #define NIC82576_CODE_EEPROM 4 #define NIC82576_CODE_INTR 5 #define NIC82576_CODE_LOOPBACK 6 #define NIC82576_CODE_CLOOPBACK 7 #define NIC82576_CODE_STRESS 7 /* Description Message */ #define NIC82576_MSG_EMDI "NIC82576 MDI test failed" #define NIC82576_MSG_ELINK "NIC82576 link test failed" #define NIC82576_MSG_EREG "NIC82576 register test failed" #define NIC82576_MSG_EEEPROM "NIC82576 EEPROM test failed" #define NIC82576_MSG_EINTR "NIC82576 interrupt test failed" #define NIC82576_MSG_ELP_PHY10 "NIC82576 10M-BaseT PHY Loopback test failed" #define NIC82576_MSG_ELP_PHY100 "NIC82576 100M-BaseT PHY Loopback test failed" #define NIC82576_MSG_ELP_PHY1000 "NIC82576 1000M-BaseT PHY Loopback test failed" #define NIC82576_MSG_ELP_EXT10 "NIC82576 10M-BaseT External Loopback test failed" #define NIC82576_MSG_ELP_EXT100 "NIC82576 100M-BaseT External Loopback test failed" #define NIC82576_MSG_ELP_EXT1000 "NIC82576 1000M-BaseT External Loopback test failed" #define NIC82576_MSG_ELP_CROSS10 "NIC82576 10M-BaseT Cross Loopback test failed" #define NIC82576_MSG_ELP_CROSS100 "NIC82576 100M-BaseT Cross Loopback test failed" #define NIC82576_MSG_ELP_CROSS1000 "NIC82576 1000M-BaseT Cross Loopback test failed" #define NIC82576_MSG_STRESS "NIC82576 stress error count" /********************************************************* * Intel Ibex-Peak (82579) Ethernet Controller *********************************************************/ /* Item */ #define NIC82579_ITEM_MDI 1 #define NIC82579_ITEM_LINK 2 #define NIC82579_ITEM_REG 3 #define NIC82579_ITEM_EEPROM 4 #define NIC82579_ITEM_INTR 5 #define NIC82579_ITEM_LOOPBACK 6 #define NIC82579_ITEM_STRESS 7 /* Error Code */ #define NIC82579_CODE_MDI 1 #define NIC82579_CODE_LINK 2 #define NIC82579_CODE_REG 3 #define NIC82579_CODE_EEPROM 4 #define NIC82579_CODE_INTR 5 #define NIC82579_CODE_LOOPBACK 6 #define NIC82579_CODE_STRESS 7 /* Description Message */ #define NIC82579_MSG_EMDI "NIC82579 MDI test failed" #define NIC82579_MSG_ELINK "NIC82579 link test failed" #define NIC82579_MSG_EREG "NIC82579 register test failed" #define NIC82579_MSG_EEEPROM "NIC82579 EEPROM test failed" #define NIC82579_MSG_EINTR "NIC82579 interrupt test failed" #define NIC82579_MSG_ELP_PHY1000 "NIC82579 1000M-BaseT PHY Loopback test failed" #define NIC82579_MSG_STRESS "NIC82377 stress error count" /* Stress */ #define NIC_BS_ITEM 10 #define NIC_BS_CODE_IOREMAP 11 #define NIC_BS_CODE_SOCKET 12 #define NIC_BS_CODE_SEND 13 #define NIC_BS_CODE_RECEIVE 14 #define NIC_BS_CODE_COMPARE 15 #define NIC_BS_MSG_IOREMAP "NIC ioremap failed" #define NIC_BS_MSG_SOCKET "NIC create socket failed" #define NIC_BS_MSG_SEND "NIC packet send failed" #define NIC_BS_MSG_RECEIVE "NIC packet receive failed" #define NIC_BS_MSG_COMPARE "NIC packet compare failed" /********************************************************* * EXPANDER FLASH & SRAM Diagnostics *********************************************************/ /* ITEM */ #define EXPANDER_FLASH_DIAG_PAGEBIT 1 //pagebit #define EXPANDER_FLASH_DIAG_WALKSEC 2 //walking sector #define EXPANDER_FLASH_DIAG_PATTERN 3 //pattem Integrity #define EXPANDER_FLASH_DIAG_WORST 4 //worst case #define EXPANDER_FLASH_DIAG_PSEUDO 5 //pseudo random #define EXPANDER_FLASH_DIAG_XX 6 #define EXPANDER_SRAM_DIAG_PATTERN 7 //pattern test #define EXPANDER_SRAM_DIAG_ADDRESS 8 //address line test #define EXPANDER_FLASH_DIAG_ADDRLINE 9 //address line test #define EXPANDER_FLASH_DIAG_DATALINE 10 //address line test /* ERROR CODE */ #define EXPANDER_FLASH_SUCCESS 0x0000 //success #define EXPANDER_FLASH_ERROR_PAGEBIT 0x0011 //pagebit #define EXPANDER_FLASH_ERROR_WALKSEC 0x0012 //walking sector #define EXPANDER_FLASH_ERROR_EWALKSEC 0x0013 //extend walking sector #define EXPANDER_FLASH_ERROR_PATTERN 0x0014 //pattem Integrity #define EXPANDER_FLASH_ERROR_WORST 0x0015 //worst case #define EXPANDER_FLASH_ERRORE_PSEUDO 0x0016 //pseudo random test #define EXPANDER_FLASH_ERROR_BACKUP 0x0017 //backup #define EXPANDER_FLASH_ERROR_RESTORE 0x0018 //restore #define EXPANDER_FLASH_ERROR_VERIFY 0x0019 //verify #define EXPANDER_SRAM_ERROR_PATTERN 0x0020 //restore #define EXPANDER_SRAM_ERROR_ADDRESS 0x0021 //verify #define EXPANDER_FLASH_ERROR_ADDRLINE 0x0022 //Address line test #define EXPANDER_FLASH_ERROR_DATALINE 0x0023 //Data line test /* Description Message */ #define EXPANDER_FLASH_ERROR_MSG_SUCESS "Success" #define EXPANDER_FLASH_ERROR_MSG_PAGEBIT "Page Bits Fail" #define EXPANDER_FLASH_ERROR_MSG_WALKSEC "Walking Sector Fail" #define EXPANDER_FLASH_ERROR_MSG_EWALKSEC "Extend Walking Sector Fail" #define EXPANDER_FLASH_ERROR_MSG_PATTERN "Pattem Integrity Fail" #define EXPANDER_FLASH_ERROR_MSG_EPATTERN "Extend Pattem Integrity Fail" #define EXPANDER_FLASH_ERROR_MSG_WORST "Worst Case Program Fail" #define EXPANDER_FLASH_ERROR_MSG_PSEUDO "Pseudo Random Program Fail" #define EXPANDER_FLASH_ERROR_MSG_BACKUP "Backup Fail" #define EXPANDER_FLASH_ERROR_MSG_RESTORE "Restore Fail" #define EXPANDER_FLASH_ERROR_MSG_VERIFY "Verify Fail" #define EXPANDER_SRAM_ERROR_MSG_PATTERN "Expander Sram Pattern Test Fail" #define EXPANDER_SRAM_ERROR_MSG_ADDRESS "Expander Sram Address Line Test Fail" #define EXPANDER_FLASH_ERROR_MSG_ADDRLINE "Expander Flash Address Line Test Fail. Line->" #define EXPANDER_FLASH_ERROR_MSG_DATALINE "Expander Flash Data Line Test Fail. Line->" /********************************************************* * LSI SAS 2008 *********************************************************/ /* ITEM */ #define LSI_2008_ITEM_1 1 #define LSI_2008_ITEM_2 2 #define LSI_2008_ITEM_3 3 #define LSI_2008_ITEM_4 4 #define LSI_2008_ITEM_5 5 #define LSI_2008_ITEM_6 6 #define LSI_2008_ITEM_7 7 #define LSI_2008_ITEM_8 8 /* Error Code */ #define LSI_2008_DIAG_CODE_11 0x0011 #define LSI_2008_DIAG_CODE_12 0x0012 #define LSI_2008_DIAG_CODE_13 0x0013 #define LSI_2008_DIAG_CODE_14 0x0014 #define LSI_2008_DIAG_CODE_15 0x0015 #define LSI_2008_DIAG_CODE_16 0x0016 #define LSI_2008_DIAG_CODE_21 0x0021 #define LSI_2008_DIAG_CODE_22 0x0021 #define LSI_2008_DIAG_CODE_31 0x0031 #define LSI_2008_DIAG_CODE_32 0x0031 #define LSI_2008_DIAG_CODE_401 0x0401 #define LSI_2008_DIAG_CODE_402 0x0402 #define LSI_2008_DIAG_CODE_403 0x0403 #define LSI_2008_DIAG_CODE_404 0x0404 #define LSI_2008_DIAG_CODE_405 0x0405 #define LSI_2008_DIAG_CODE_406 0x0406 #define LSI_2008_DIAG_CODE_407 0x0407 #define LSI_2008_DIAG_CODE_408 0x0408 #define LSI_2008_DIAG_CODE_409 0x0409 #define LSI_2008_DIAG_CODE_40A 0x040A #define LSI_2008_DIAG_CODE_40B 0x040B #define LSI_2008_DIAG_CODE_40C 0x040C #define LSI_2008_DIAG_CODE_501 0x0501 #define LSI_2008_DIAG_CODE_502 0x0502 #define LSI_2008_DIAG_CODE_503 0x0503 #define LSI_2008_DIAG_CODE_504 0x0504 #define LSI_2008_DIAG_CODE_505 0x0505 #define LSI_2008_DIAG_CODE_506 0x0506 #define LSI_2008_DIAG_CODE_507 0x0507 #define LSI_2008_DIAG_CODE_508 0x0508 #define LSI_2008_DIAG_CODE_61 0x0061 #define LSI_2008_DIAG_CODE_71 0x0071 #define LSI_2008_DIAG_CODE_81 0x0081 /* Description Message */ #define LSI_2008_DIAG_ERR_MSG_11 "Fail to alloc memory from kernel" #define LSI_2008_DIAG_ERR_MSG_12 "IOC Memory Data Mismatch" #define LSI_2008_DIAG_ERR_MSG_13 "IOC Memory Parity Error" #define LSI_2008_DIAG_ERR_MSG_14 "IOC Internal Memory Test Failed" #define LSI_2008_DIAG_ERR_MSG_15 "IOC External Memory Test Failed" #define LSI_2008_DIAG_ERR_MSG_16 "Failed to find IOC" #define LSI_2008_DIAG_ERR_MSG_21 "Fail to io map diagnostic memory" #define LSI_2008_DIAG_ERR_MSG_22 "Failed to find IOC" #define LSI_2008_DIAG_ERR_MSG_31 "IOC No Interrupts Detected" #define LSI_2008_DIAG_ERR_MSG_32 "Failed to find IOC" #define LSI_2008_DIAG_ERR_MSG_401 "IOC Reply Data Mismatch" #define LSI_2008_DIAG_ERR_MSG_402 "Fail to alloc msg frames" #define LSI_2008_DIAG_ERR_MSG_403 "Fail to alloc pci memory" #define LSI_2008_DIAG_ERR_MSG_404 "SMP Report General Command time Out" #define LSI_2008_DIAG_ERR_MSG_405 "SMP Passthru: oh no, there is no reply" #define LSI_2008_DIAG_ERR_MSG_406 "IOC Initialization Failed" #define LSI_2008_DIAG_ERR_MSG_407 "Get Phy Configuration Error" #define LSI_2008_DIAG_ERR_MSG_408 "Fail to Initialize with new Phy configuration" #define LSI_2008_DIAG_ERR_MSG_409 "IOC Configuration Error" #define LSI_2008_DIAG_ERR_MSG_40A "IOC Error Reading Expander SAS Address" #define LSI_2008_DIAG_ERR_MSG_40B "Phy Test Fail " #define LSI_2008_DIAG_ERR_MSG_40C "Failed to find IOC" #define LSI_2008_DIAG_ERR_MSG_501 "IOC Initialization Failed" #define LSI_2008_DIAG_ERR_MSG_502 "IOC Get Phy Configuration Failed" #define LSI_2008_DIAG_ERR_MSG_503 "Fail to Initialize with new Phy configuration" #define LSI_2008_DIAG_ERR_MSG_504 "IOC Configuration Error" #define LSI_2008_DIAG_ERR_MSG_505 "IOC Get Target Info Failed" #define LSI_2008_DIAG_ERR_MSG_506 "IOC Data Mismatch During I/O WriteBuffer" #define LSI_2008_DIAG_ERR_MSG_507 "Loopback Test Fail " #define LSI_2008_DIAG_ERR_MSG_508 "Failed to find IOC" #define LSI_2008_DIAG_ERR_MSG_61 "Failed to find IOC" #define LSI_2008_DIAG_ERR_MSG_71 "Failed to find IOC" #define LSI_2008_DIAG_ERR_MSG_81 "Failed to find IOC" /********************************************************* * LSI SAS x36 Expander *********************************************************/ /* ITEM */ #define LSI_EXPANDER_ITEM_1 1 /* Error Code */ #define LSI_EXPANDER__DIAG_CODE_11 0x0011 #define LSI_EXPANDER__DIAG_CODE_12 0x0012 #define LSI_EXPANDER__DIAG_CODE_13 0x0013 #define LSI_EXPANDER__DIAG_CODE_14 0x0014 /* Description Message */ #define LSI_EXPANDER__DIAG_ERR_MSG_11 "Found Jitter error count on PHY" #define LSI_EXPANDER__DIAG_ERR_MSG_12 "Found DISPARITY on PHY" #define LSI_EXPANDER__DIAG_ERR_MSG_13 "Rx jitter pattern mismatch" #define LSI_EXPANDER__DIAG_ERR_MSG_14 "Pattern type is illegal" /********************************************************* * Board Stress *********************************************************/ #define BOARD_STRESS_SAS_ERROR 1<<0 #define BOARD_STRESS_QE8_ERROR 1<<1 #define BOARD_STRESS_IB_ERROR 1<<2 #define BOARD_STRESS_ETH0_ERROR 1<<3 #define BOARD_STRESS_ETH1_ERROR 1<<4 #define BOARD_STRESS_ETH2_ERROR 1<<5 #define BOARD_STRESS_PCH_I2C_ERROR 1<<6 #define BOARD_STRESS_FPGA_I2C_ERROR 1<<7 #define BOARD_STRESS_XOR_ERROR 1<<8 #define BOARD_STRESS_COPY_ERROR 1<<9 #define BOARD_STRESS_PLX_ERROR 1<<10 #endif //__INCcommMEC