/**************************************************************************** * * * Copyright 2004-2011 NetApp Inc. All rights reserved. This file is * * confidential and a trade secret of NetApp Inc. The receipt or * * possession of this file does not convey any rights to reproduce or * * disclose its contents or to manufacture, use, or sell anything it may * * describe, in whole, or in part, without the specific written consent of * * LSI Corporation. * * * ****************************************************************************/ /**************************************************************************** * * * NAME i2c-zebulon.h * * SUMMARY * * VERSION %version: % * * UPDATE DATE %date_modified: % * * PROGRAMMER %created_by: Merck Hung % * * * * Copyright 2002-2011 NetApp Inc. All Rights Reserved. * * * * DESCRIPTION: * * * ****************************************************************************/ /******************************************************************************* NAME $RCSfile: i2c-zebulon.h,v $ SUMMARY Header file of LSI Zebulon FPGA I2C Bus Driver VERSION $Revision: 1.2 $ UPDATE DATE $Date: 2009/08/03 08:34:02 $ PROGRAMMER $Author: cloud $ Copyright 2009 LSI Corporation. All Rights Reserved. DESCRIPTION: REFERENCE: *******************************************************************************/ #ifndef INCi2c_zebulon #define INCi2c_zebulon /* Type Definition */ typedef unsigned long ULONG; #define TRUE 1 #define FALSE 0 #define OK 0 #define ERROR -1 #define ZEBULON_I2C_MASTER_OFFSET 0x00000100 #define ZEBULON_I2C_MASTER_MAP_SIZE 256 #define ZEBULON_I2C_CLK_100MHZ 100 #define ZEBULON_I2C_CLK_400MHZ 400 #define ZEBULON_I2C_BUS_NUM 4 #define ZEBULON_I2C_BUS_0 0 #define ZEBULON_I2C_BUS_1 1 #define ZEBULON_I2C_BUS_2 2 #define ZEBULON_I2C_BUS_3 3 /*** MACRO DEFINITIONS ***/ #define delayMicroseconds msleep #define SOFT_RESET() base->ISR = 0x01 #define I2C_LSI_BUS_RESET_DELAY() delayMicroseconds(100) #define I2C_BUS_COMPLETE_DELAY() delayMicroseconds(5) #define CHECK_BIT(bit, value) (value & bit) #define DQ_WRITE_LSIL(fmt, id, args...) /* The following are the desired frequencies to run I2C bus at 100K */ #define I2C_DESIRED_SCL_HIGH_RATE_100 200803 /* Desired time is 4980 nano secs */ #define I2C_DESIRED_SCL_LOW_RATE_100 200803 /* Desired time is 4980 nano secs */ #define I2C_DESIRED_SPIKE_FILTER_RATE_100 2222222 /* Desired time is 450 nano secs */ #define I2C_DESIRED_SDA_SETUP_RATE_100 3333333 /* Desired time is 300 nano secs */ #define I2C_DESIRED_SDA_HOLD_RATE_100 877190 /* Desired time is 1140 nano secs */ /* The following are the desired frequencies to run I2C bus at 400K */ #define I2C_DESIRED_SCL_HIGH_RATE_400 833333 /* Desired time is 1200 nano secs */ #define I2C_DESIRED_SCL_LOW_RATE_400 833333 /* Desired time is 1200 nano secs */ #define I2C_DESIRED_SPIKE_FILTER_RATE_400 2222222 /* Desired time is 450 nano secs */ #define I2C_DESIRED_SDA_SETUP_RATE_400 16666666 /* Desired time is 75 nano secs */ #define I2C_DESIRED_SDA_HOLD_RATE_400 3333333 /* Desired time is 300 nano secs */ #define I2C_PCLK 33333333 /* 33 MHz */ #define SCL_HIGH_PERIOD_100 (I2C_PCLK / I2C_DESIRED_SCL_HIGH_RATE_100) #define SCL_LOW_PERIOD_100 (I2C_PCLK / I2C_DESIRED_SCL_LOW_RATE_100) #define SPIKE_FILTER_CONTROL_100 (I2C_PCLK / I2C_DESIRED_SPIKE_FILTER_RATE_100) #define SDA_SETUP_TIME_100 (I2C_PCLK / I2C_DESIRED_SDA_SETUP_RATE_100) #define SDA_HOLD_TIME_100 (I2C_PCLK / I2C_DESIRED_SDA_HOLD_RATE_100) #define SCL_HIGH_PERIOD_400 (I2C_PCLK / I2C_DESIRED_SCL_HIGH_RATE_400) #define SCL_LOW_PERIOD_400 (I2C_PCLK / I2C_DESIRED_SCL_LOW_RATE_400) #define SPIKE_FILTER_CONTROL_400 (I2C_PCLK / I2C_DESIRED_SPIKE_FILTER_RATE_400) #define SDA_SETUP_TIME_400 (I2C_PCLK / I2C_DESIRED_SDA_SETUP_RATE_400) #define SDA_HOLD_TIME_400 (I2C_PCLK / I2C_DESIRED_SDA_HOLD_RATE_400) #define MAX_LSI_I2C_RETRIES 5 #define I2C_GLOBAL_CONTROL 0x00 /* I2C Global Control Register */ #define I2C_INTERRUPT_STATUS 0x04 /* I2C Interrupt Status Register */ #define I2C_INTERRUPTS_ENABLE 0x08 /* I2C Interrupt Enable Register */ #define I2C_WAIT_TIMER_CONTROL 0x0c /* I2C Wait TImer Control Register */ #define I2C_IBML_TIMEOUT 0x10 /* I2C IBML t_TIMEOUT Control Register */ #define I2C_IBML_LOW_MEXT 0x14 /* I2C IBML t_LOW:MEXT Control Register */ #define I2C_IBML_LOW_SEXT 0x18 /* I2C IBML t_LOW:SEXT Control Register */ #define I2C_TMR_CLOCK_DIV_CTRL 0x1c /* I2C Timer Clock Divider Control Register */ #define I2C_MTR 0x20 /* I2C Monitor Register */ #define I2C_SOFT_RESET 0x24 /* I2C Soft Reset Register */ #define I2C_MASTER_COMMAND 0x28 /* I2C Master Command Register */ #define I2C_MASTER_RTL 0x2c /* I2C Master Receive Transfer Length Register */ #define I2C_MASTER_TTL 0x30 /* I2C Master Transmit Transfer Length Register */ #define I2C_MASTER_AR1 0x34 /* I2C Master Address Register 1 */ #define I2C_MASTER_AR2 0x38 /* I2C Master Address Register 2 */ #define I2C_MASTER_DATA 0x3c /* I2C Master Data Register */ #define I2C_MASTER_TX_FIFO_STAT 0x40 /* I2C Master Transmit FIFO Status Register */ #define I2C_MASTER_RX_FIFO_STAT 0x44 /* I2C Master Receive FIFO Status Register */ #define I2C_MASTER_INT_ENABLE 0x48 /* I2C Master Interrupt Enable Register */ #define I2C_MASTER_INT_STATUS 0x4c /* I2C Master Interrupt Status Register */ #define I2C_MASTER_TX_BYTE 0x50 /* I2C Master Transmit Bytes Transferred Register */ #define I2C_MASTER_RX_BYTE 0x54 /* I2C Master Reveive Bytes Transferred Register */ #define I2C_SLAVE_ADDR_DC 0x58 /* I2C Slave Address decode control Register */ #define I2C_SLAVE_ADDR1 0x5c /* I2C Slave Address 1 Register */ #define I2C_SLAVE_ADDR2 0x60 /* I2C Slave Address 2 Register */ #define I2C_SLAVE_RX_CONTROL 0x64 /* I2C Slave RX Control Register */ #define I2C_SLAVE_DATA 0x68 /* I2C Slave Data Register */ #define I2C_SLAVE_RX_FIFO_STAT 0x6c /* I2C Slave Receive FIFO Status Register */ #define I2C_SLAVE_INT_ENABLE 0x70 /* I2C Slave Interrupt Enable Register */ #define I2C_SLAVE_INT_STATUS 0x74 /* I2C Slave Interrupt Status Register */ #define I2C_SLAVE_READ_DUMMY 0x78 /* I2C Slave read dummy byte Register */ #define NOT_IN_USE 0x7c /* I2C Unused Register */ #define I2C_SCL_HIGH_PERIOD 0x80 /* I2C SCL High Period Register */ #define I2C_SCL_LOW_PERIOD 0x84 /* I2C SCL Low Period Register */ #define I2C_SPIKE_FILTER_CTRL 0x88 /* I2C Spike Filter Control Register */ #define I2C_SDA_SETUP_TIME 0x8c /* I2C SDA Setup Time Register */ #define I2C_SDA_HOLD_TIME 0x90 /* I2C SDA Hold Time Register */ /* Master Control Register Commands */ #define ISSUE_COMMAND 0x08 #define FLUSH_MASTER_TX_FIFO 0x07 #define ISSUE_MASTER_STOP 0x03 #define SEQUENCE_MODE_TRANSFER 0x02 #define AUTOMATIC_MODE_TRANSFER 0x01 #define MANUAL_MODE_TRANSFER 0x00 /* Global Control Register Values */ #define ENABLE_IBML 0x04 #define ENABLE_SLAVE 0x02 #define ENABLE_MASTER 0x01 /* Global I2C Monitor Register Values */ #define SCL_STATUS 0x01 #define SDA_STATUS 0x02 #define SCL_CONTROL 0x04 #define SDA_CONTROL 0x08 #define SCL_EDGE 0x10 #define SDA_EDGE 0x20 /* Interrupt Enable Register Values */ #define SLAVE_INTERRUPT_ENABLE 0x02 #define MASTER_INTERRUPT_ENABLE 0x01 /* Master Interrupts */ #define IBML_TIMEOUT 0x8000 #define IBML_LOW_MEXT 0x4000 #define RX_FIFO_HIGH_THRESHOLD_REACHED 0x2000 #define TX_FIFO_LOW_THRESHOLD_REACHED 0x1000 #define TRANSFER_COMPLETED_STOP_NOT_SENT 0x0800 #define TRANSFER_COMPLETED_STOP_SENT 0x0400 #define STOP_COMMAND_COMPLETED 0x0200 #define ILLEGAL_PARAMETER 0x0100 #define TIMEOUT_OCCURRED_STOP_SENT 0x0080 #define ARBITRATION_LOST 0x0040 #define NAK_RECEIVED_DURING_TX_DATA_PHASE 0x0020 #define NAK_RECEIVED_DURING_ADDR_PHASE 0x0010 #define TRANSFER_STOPPED 0x0008 #define SEQUENCE_TRANSFER_IN_PROGRESS 0x0004 #define TX_TRANSFER_IN_PROGRESS 0x0002 #define RX_TRANSFER_IN_PROGRESS 0x0001 //typedef struct lsiI2c_32bits struct lsiI2c_32bits { volatile UINT8 IGC; /* Global Control */ volatile UINT8 IGC_pad[3]; volatile UINT8 IIS; /* Interrupt Status */ volatile UINT8 IIS_pad[3]; volatile UINT8 IIE; /* Interrupt Enable */ volatile UINT8 IIE_pad[3]; volatile UINT16 IWTC; /* Wait Timer Control */ volatile UINT16 IWTC_pad; volatile UINT16 IIT; /* IBML Timeout Control */ volatile UINT16 IIT_pad; volatile UINT16 IILM; /* IBML Low MExt Control */ volatile UINT16 IILM_pad; volatile UINT16 IILS; /* IBML Low SExt Control */ volatile UINT16 IILS_pad; volatile UINT8 ITCDC; /* Timer Clock Divider Control */ volatile UINT8 ITCDC_pad[3]; volatile UINT8 IM; /* I2C Monitor */ volatile UINT8 IM_pad[3]; volatile UINT16 ISR; /* Soft Reset */ volatile UINT16 ISR_pad; volatile UINT8 IMC; /* Master Command */ volatile UINT8 IMC_pad[3]; volatile UINT8 IMRTL; /* Master Receive Transfer Length */ volatile UINT8 IMRTL_pad[3]; volatile UINT8 IMTTL; /* Master Transmit Transfer Length */ volatile UINT8 IMTTL_pad[3]; volatile UINT8 IMAR1; /* Master Address Register 1 */ volatile UINT8 IMAR1_pad[3]; volatile UINT8 IMAR2; /* Master Address Register 2 */ volatile UINT8 IMAR2_pad[3]; volatile UINT8 IMD; /* Master Data */ volatile UINT8 IMD_pad[3]; volatile UINT8 IMTFS; /* Master Transmit FIFO Status */ volatile UINT8 IMTFS_pad[3]; volatile UINT8 IMRFS; /* Master Receive FIFO Status */ volatile UINT8 IMRFS_pad[3]; volatile UINT16 IMIE; /* Master Interrupt Enable */ volatile UINT16 IMIE_pad; volatile UINT32 IMIS; /* Master Interrupt Status */ volatile UINT8 IMTB; /* Master Transmit Bytes Transfer */ volatile UINT8 IMTB_pad[3]; volatile UINT8 IMRB; /* Master Receive Bytes Transfer */ volatile UINT8 IMRB_pad[3]; volatile UINT8 ISADC; /* Slave Address Decode Control */ volatile UINT8 ISADC_pad[3]; volatile UINT16 ISA1; /* Slave Address 1 */ volatile UINT16 ISA1_pad; volatile UINT16 ISA2; /* Slave Address 2 */ volatile UINT16 ISA2_pad; volatile UINT8 ISRC; /* Slave RX Control */ volatile UINT8 ISRC_pad[3]; volatile UINT8 ISD; /* Slave Data */ volatile UINT8 ISD_pad[3]; volatile UINT8 ISRFS; /* Slave Receive FIFO Status */ volatile UINT8 ISRFS_pad[3]; volatile UINT16 ISIE; /* Slave Interrupt Enable */ volatile UINT16 ISIE_pad; volatile UINT16 ISIS; /* Slave Interrupt Status */ volatile UINT16 ISIS_pad; volatile UINT8 ISRD; /* Slave Read Dummy Byte */ volatile UINT16 ISRD_pad; volatile UINT32 NIU; /* Unused */ volatile UINT16 ISHP; /* SCL High Period */ volatile UINT16 ISHP_pad; volatile UINT16 ISLP; /* SCL Low Period */ volatile UINT16 ISLP_pad; volatile UINT8 ISFC; /* Spike Filter Length */ volatile UINT8 ISFC_pad[3]; volatile UINT16 ISST; /* SDA Setup Time */ volatile UINT16 ISST_pad; volatile UINT16 ISHT; /* SDA Hold Time */ volatile UINT16 ISHT_pad; }; struct lsiI2c_16bits { volatile UINT16 IGC; volatile UINT16 IIS; volatile UINT16 IIE; volatile UINT16 IWTC; volatile UINT16 IIT; volatile UINT16 IILM; volatile UINT16 IILS; volatile UINT16 ITCDC; volatile UINT16 IM; volatile UINT16 ISR; volatile UINT16 IMC; volatile UINT16 IMRTL; volatile UINT16 IMTTL; volatile UINT16 IMAR1; volatile UINT16 IMAR2; volatile UINT16 IMD; volatile UINT16 IMTFS; volatile UINT16 IMRFS; volatile UINT16 IMIE; volatile UINT16 IMIS; volatile UINT16 IMTB; volatile UINT16 IMRB; volatile UINT16 ISADC; volatile UINT16 ISA1; volatile UINT16 ISA2; volatile UINT16 ISRC; volatile UINT16 ISD; volatile UINT16 ISRFS; volatile UINT16 ISIE; volatile UINT16 ISIS; volatile UINT16 ISRD; volatile UINT16 NIU; volatile UINT16 ISHP; volatile UINT16 ISLP; volatile UINT16 ISFC; volatile UINT16 ISST; volatile UINT16 ISHT; }; #define Platform_I2C_REG_DELTA 0 #if Platform_I2C_REG_DELTA == 2 #define LSI_I2C struct lsiI2c_16bits #else #define LSI_I2C struct lsiI2c_32bits #endif #define I2C_DATA_BUFFER_SIZE 256 typedef struct { void *baseAddr; ULONG busRate; UINT8 busNumber; UINT8 i2cTarget; UINT8 i2cRegAddr; UINT16 regAddr; UINT8 i2cTransferInProgress; UINT8 i2cByteTimeout; ULONG i2cCommandType; ULONG i2cSendCount; ULONG i2cReceiveCount; UINT8 *i2cReceiveBuffer; UINT8 i2cSendBuffer[I2C_DATA_BUFFER_SIZE]; ULONG i2cBytesSent; UINT16 i2cStatus; ULONG i2cDataDirection; ULONG i2cDataIndex; ULONG i2cIntCount; UINT8 deviceUnresponsive; UINT64 startTime; UINT64 endTime; wait_queue_head_t i2cWaitQueue; UINT8 i2cWaitDone; } I2C_BUS_MASTER_INFO; /* Flag definitions for the i2c packet */ typedef enum { I2C_WRITE = 0x0000, I2C_READ = 0x0001, I2C_NO_REG_ADDR = 0x0002, I2C_DUAL_BYTE_ADDR = 0x0004, I2C_PF_IGNORE = 0x0008, I2C_10BIT = 0x0010 } I2C_PACKET_FLAGS; typedef struct i2cPacket { UINT8 *dataPtr; #if defined(CHASSIS_WSAS) UINT8 *sdataPtr; #endif UINT8 busNumber; UINT8 i2cAddr; I2C_PACKET_FLAGS flags; UINT16 regAddr; UINT16 numBytes; #if defined(CHASSIS_WSAS) UINT16 snumBytes; #endif } I2C_PACKET; #endif /* INCi2c_zebulon */