/* * Copyright (c) 2011-2015, Emulex * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. Neither the name of the copyright holder nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * */ #if !defined(__ELXU_SLI4_H__) #define __ELXU_SLI4_H__ #include #define SLI4_PCI_SOFT_RESET_CSR 0x005c #define SLI4_PCI_SOFT_RESET_MASK 0x0080 #define SLI4_PHYSDEV_CONTROL 0x0414 #define SLI4_PHYSDEV_CONTROL_FRST 0x02 #define SLI4_PHYSDEV_CONTROL_DD 0x04 #define SLI4_PHYSDEV_CONTROL_FRL_MASK 0x00f0 #define SLI4_SLIPORT_STATUS 0x0404 #define SLI4_SLIPORT_STATUS_RDY (0x1 << 23) #define SLI4_SLIPORT_SEMAPHORE_LAN 0x400 #define SLI4_SLIPORT_SEMAPHORE_SH 0xac #define SLI4_SLIPORT_PORT_STATUS_MASK 0xffff #define SLI4_PORT_READY 0xc000 #define SLI4_BMBX 0x0160 #define SLI4_BMBX_RDY 0x01 #define SLI4_SLIPORT_CONTROL 0x408 #define SLI4_SLIPORT_CONTROL_IP (0x1 << 27) // Mailbox commands #define MBOX_SLI_CONFIG 0x9B #define MBOX_READ_STATUS 0x0E #define MBOX_READ_REV 0x11 #define MBOX_READ_LNK_STAT 0x12 #define MBOX_WRITE_NVPARMS 0x03 #define MBOX_READ_NVPARMS 0x02 #define MBOX_SET_LINK_DIAG_STATE 0x22 #define MBOX_SET_DPORT_MODE 0x27 #define MBOX_GET_DPORT_RESULTS 0x28 #define MBOX_RUN_BIU_DIAG 0x84 // ======== Subsystems and Opcodes used by the MBOX_SLI_CONFIG command ======== // Common Mailbox subsystems #define MBOX_SUBSYSTEM_COMMON 0x1 #define MBOX_SUBSYSTEM_FCOE 0xC // Common Mailbox opcodes #define OPCODE_COMMON_READ_FLASHROM 0x06 // Skyhawk only #define OPCODE_COMMON_WRITE_FLASHROM 0x07 // Skyhawk only #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 0x20 #define OPCODE_COMMON_GET_FAT 0x28 // Skyhawk only #define OPCODE_COMMON_ENABLE_DISABLE_PORT 0x3e // iSCSI only #define OPCODE_COMMON_GET_BE_CONFIGURATION_AND_RESOURCES 0x51 // iSCSI only #define OPCODE_COMMON_SET_BE_CONFIGURATION_AND_RESOURCES 0x52 // iSCSI only #define OPCODE_COMMON_MANAGE_FAT 0x44 // Skyhawk only #define OPCODE_COMMON_READ_TRANCEIVER_DATA 0x49 // Skyhawk only #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES 0x7D // Skyhawk only #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES 0x7E // Skyhawk only #define OPCODE_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7F // Skyhawk only #define OPCODE_COMMON_EXT_FAT_RETRIEVE_SHAPSHOT 0x80 // Skyhawk only #define OPCODE_COMMON_EXT_FAT_READ_STRING_TABLE 0x82 // Skyhawk only #define OPCODE_COMMON_GET_FUNCTION_CONFIG 0xa0 #define OPCODE_COMMON_GET_PROFILE_CONFIG 0xa4 #define OPCODE_COMMON_SET_PROFILE_CONFIG 0xa5 #define OPCODE_COMMON_GET_PROFILE_LIST 0xa6 #define OPCODE_COMMON_GET_ACTIVE_PROFILE 0xa7 #define OPCODE_COMMON_SET_ACTIVE_PROFILE 0xa8 #define OPCODE_COMMON_READ_OBJECT 0xAB // Lancer only #define OPCODE_COMMON_WRITE_OBJECT 0xAC // Lancer only #define OPCODE_COMMON_READ_OBJECT_LIST 0xAD // Lancer only #define OPCODE_COMMON_DELETE_OBJECT 0xAE // Lancer only #define OPCODE_COMMON_GET_RECONFIG_LINK_INFO 0xC9 // Skyhawk only #define OPCODE_COMMON_SET_RECONFIG_LINK_INFO 0xCA // Skyhawk only #define OPCODE_COMMON_SET_DUMP_LOCATION 0xB8 // Lancer Only // Common iSCSI mailbox subsystem #define MBOX_SUBSYSTEM_COMMON_ISCSI 0x02 // Common iSCSI mailbox commands #define OPCODE_COMMON_ISCSI_SET_TCP_PARAMETERS 0x48 #define OPCODE_COMMON_ISCSI_CONNECTION_UPDATE 0x49 #define OPCODE_COMMON_ISCSI_GET_CONNECTION_INFO 0x4a // DMTF Mailbox subsystem #define MBOX_SUBSYSTEM_DMTF 0x11 // DMTF Mailbox commands #define OPCODE_DMTF_EXEC_CLP_CMD 0x01 #define MBOX_ENTRY_LENGTH 256 // mbox_sge_t - SGE used by SLI_CONFIG commands typedef struct { uint32_t address_low; uint32_t address_high; unsigned length:24; unsigned :8; } mbox_sge_t; // mbox_hbd_t - Host Buffer Descripitor typedef struct { unsigned buffer_length:24; unsigned :8; uint32_t buffer_address_low; uint32_t buffer_address_high; } mbox_hbd_t; // Generic Mailbox Command typedef union { struct { uint32_t :8; uint32_t command:8; uint32_t :16; uint32_t payload[63]; } request; struct { uint32_t :8; uint32_t command:8; uint32_t status:16; uint32_t payload[63]; }response; } mbox_command_t; // mbox_sli_config_t - SLI_CONFIG data typedef struct { unsigned reserved:8; unsigned command:8; unsigned status:16; unsigned emb:1; unsigned :2; unsigned pcmd_count:5; unsigned :24; uint32_t payload_length; uint32_t tag_lo; uint32_t tag_hi; unsigned :32; mbox_sge_t sge[0]; } mbox_sli_config_t; typedef struct{ unsigned reserved:8; unsigned command:8; unsigned status:16; uint32_t :16, sli_level:4, fcoem:1, ceev:2, :6, vpd:1, :2; uint32_t first_hw_revision; uint32_t second_hw_revision; uint32_t rsvd4; uint32_t third_hw_revision; uint32_t fc_ph_low:8, fc_ph_high:8, feature_level_low:8, feature_level_high:8; uint32_t rsvd7; uint32_t first_fw_id; char first_fw_name[16]; uint32_t second_fw_id; char second_fw_name[16]; uint32_t rsvd18[30]; uint32_t available_length:24, :8; uint32_t physical_address_low; uint32_t physical_address_high; uint32_t returned_vpd_length; uint32_t actual_vpd_length; } mbox_read_rev_t; typedef struct{ unsigned :8; unsigned command:8; unsigned status:16; unsigned cc:1; unsigned :15; unsigned :32; uint32_t transmit_kbyte_count; uint32_t receive_kbyte_count; uint32_t transmit_frame_count; uint32_t receive_frame_count; uint32_t transmit_sequence_count; uint32_t receive_sequence_count; uint32_t total_exchanges_originator; uint32_t total_exchanges_responder; uint32_t receive_p_bsy_count; uint32_t receive_f_bsy_count; uint32_t dropped_frames_due_to_no_rq_buffer_count; uint32_t empty_rq_timeout_count; uint32_t dropped_frames_due_to_no_xri_count; uint32_t empty_xri_pool_count; } mbox_read_status_t; typedef struct { // word 0 is common unsigned :8; unsigned command:8; unsigned status:16; // word 1 uint32_t rec:1; uint32_t gec:1; uint32_t w02of:1; uint32_t w03of:1; uint32_t w04of:1; uint32_t w05of:1; uint32_t w06of:1; uint32_t w07of:1; uint32_t w08of:1; uint32_t w09of:1; uint32_t w10of:1; uint32_t w11of:1; uint32_t w12of:1; uint32_t w13of:1; uint32_t w14of:1; uint32_t w15of:1; uint32_t w16of:1; uint32_t w17of:1; uint32_t w18of:1; uint32_t w19of:1; uint32_t w20of:1; uint32_t w21of:1; uint32_t :8; uint32_t clrc:1; uint32_t clof:1; uint32_t link_failure_error_count; uint32_t loss_of_sync_error_count; uint32_t loss_of_signal_error_count; uint32_t primitive_sequence_error_count; uint32_t invalid_transmission_word_error_count; uint32_t crc_error_count; uint32_t primitive_sequence_event_timeout_count; uint32_t elastic_buffer_overrun_error_count; uint32_t arbitration_timeout_count; uint32_t advertised_receive_buffer_to_buffer_credit; uint32_t current_receive_buffer_to_buffer_credit; uint32_t advertised_transmit_buffer_to_buffer_credit; uint32_t current_transmit_buffer_to_buffer_credit; uint32_t received_eofa_count; uint32_t received_eofdti_count; uint32_t received_eofni_count; uint32_t received_soff_count; uint32_t received_dropped_no_aer_count; uint32_t received_dropped_no_available_rpi_resources_count; uint32_t received_dropped_no_available_xri_resources_count; uint32_t fec_corrected_blocks_count; uint32_t fec_uncorrectable_blocks_count; uint32_t lrr_count_local; uint32_t lr_count_remote; } mbox_read_link_status_t; typedef struct sli4_req_hdr_s { uint32_t opcode:8, subsystem:8, :16; uint32_t timeout; uint32_t request_length; uint32_t version:8, :24; }sli4_req_hdr_t; typedef struct sli4_run_biu_diag_hdr_s { uint32_t :8, command:8, status:16; uint32_t rsvd; } sli4_run_biu_diag_hdr_t; typedef struct sli4_res_hdr_s { uint32_t opcode:8, subsystem:8, :16; uint32_t status:8, additional_status:8, :16; uint32_t response_length; uint32_t actual_response_length; }sli4_res_hdr_t; typedef struct mbox_req_fcoe_set_link_diag_state_s { sli4_req_hdr_t hdr; uint32_t diag:1, shrd:1, div:1, shv:1, :12, link_number:6, link_type:2, :8; }mbox_req_fcoe_set_link_diag_state_t; typedef struct mbox_res_fcoe_set_link_diag_state_s { sli4_res_hdr_t hdr; }mbox_res_fcoe_set_link_diag_state_t; typedef struct mbox_req_run_biu_diag_s { sli4_run_biu_diag_hdr_t hdr; uint32_t tx_buf_len:24, tx_buf_flags:8; uint32_t tx_phy_add_low; uint32_t tx_phy_add_high; uint32_t rx_buf_len:24, rx_buf_flags:8; uint32_t rx_phy_add_low; uint32_t rx_phy_add_high; } mbox_req_run_biu_diag_t; typedef struct mbox_req_fcoe_set_dport_mode_s { sli4_req_hdr_t hdr; uint32_t stop:1, dport_mode:3, enable:1, :27; uint32_t link_number:6, link_type:2, test_bitmask:8, pre_defined_pattern:16; uint32_t frame_size:16, frame_count:16; uint32_t user_defined_payload; uint32_t test_duration; }mbox_req_fcoe_set_dport_mode_t; typedef struct mbox_res_fcoe_set_dport_mode_s { sli4_res_hdr_t hdr; uint32_t ev:1, enabled:1, :30; }mbox_res_fcoe_set_dport_mode_t; typedef struct mbox_req_fcoe_get_dport_results_s { sli4_req_hdr_t hdr; uint32_t link_number:6, link_type:2, query_type:1, :23; }mbox_req_fcoe_get_dport_results_t; typedef struct fcoe_test_result_descriptor_s { uint32_t test_phase_result:8, test_phase:8, err:1, :15; uint32_t w1; uint32_t w2; } fcoe_test_result_descriptor_t; typedef struct mbox_res_fcoe_get_dport_results_s { sli4_res_hdr_t hdr; uint32_t overall_test_result:8, num_phases:8, :14, remote:1, local:1; uint32_t round_trip_latency; uint32_t link_distance; uint16_t frame_size; uint16_t buffers_required; fcoe_test_result_descriptor_t trd[6]; }mbox_res_fcoe_get_dport_results_t; typedef struct { uint32_t :8, command:8, status:16; uint32_t rsvd1[4]; uint8_t wwpn[8]; uint8_t wwnn[8]; uint32_t hard_alpa:8, preferred_d_id:24; } mbox_rw_nvparms_t; // P.37 // 5.3.1 Mailbox Command/Response Header // // only for SLI_CONFIG family mailbox commands // // common mailbox header typedef struct { uint32_t opcode:8; uint32_t subsystem:8; uint32_t :16; union { struct { uint32_t timeout; // (out) timeout (in) status/add'l status } out; struct { uint32_t status:8; uint32_t additional_status:8; uint32_t :16; } in; } word1; uint32_t request_length; uint32_t actual_response_length; } mbox_common_t; // 6.6 READ_COMMON_FLASHROM typedef struct { mbox_common_t common; uint32_t flashrom_access_op_code; #define MGMT_FLASHROM_OPCODE_FLASH 0x1 #define MGMT_FLASHROM_OPCODE_SAVE 0x2 #define MGMT_FLASHROM_OPCODE_CLEAR 0x3 #define MGMT_FLASHROM_OPCODE_REPORT 0x4 #define MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x5 #define MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x6 #define MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x7 #define MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x8 uint32_t flashrom_access_op_type; #define MGMT_FLASHROM_OPTYPE_CODE_FIRMWARE 0x0 #define MGMT_FLASHROM_OPTYPE_CODE_REDBOOT 0x1 #define MGMT_FLASHROM_OPTYPE_CODE_BIOS 0x2 #define MGMT_FLASHROM_OPTYPE_CODE_PXE_BIOS 0x3 #define MGMT_FLASHROM_OPTYPE_CODE_CTRLS 0x4 #define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 0x5 #define MGMT_FLASHROM_OPTYPE_CFG_INI 0x6 #define MGMT_FLASHROM_OPTYPE_ROM_OFFSET_SPECIFIED 0x7 #define MGMT_FLASHROM_OPTYPE_CODE_FCOE_BIOS 0x8 #define MGMT_FLASHROM_OPTYPE_CODE_iSCSI_FW_BACKUP 0x9 #define MGMT_FLASHROM_OPTYPE_CODE_FCOE_FW_ACTIVE 0xa #define MGMT_FLASHROM_OPTYPE_CODE_FCOE_FW_BACKUP 0xb #define MGMT_FLASHROM_OPTYPE_CODE_CTRLP 0xc #define MGMT_FLASHROM_OPTYPE_CODE_NCSI_FW 0xd uint32_t data_buffer_size; uint32_t offset; uint32_t data_buffer[0]; } mbox_common_read_flashrom_t; typedef mbox_common_read_flashrom_t mbox_common_write_flashrom_t; // mbox_common_get_fat typedef struct { mbox_common_t common; union { struct { uint32_t clear_log:8; uint32_t num_pages:8; uint32_t page_offset:16; uint64_t buffer_addr[27]; } request; struct { uint32_t log_size; uint32_t bytes_transferred; } response; } params; } mbox_common_get_fat_t; // mbox_common_manage_fat typedef struct { mbox_common_t common; union { struct { uint32_t fat_operation; #define FAT_OPERATION_RETRIEVE 0x0 #define FAT_OPERATION_QUERY 0x1 #define FAT_OPERATION_CLEAR 0x2 #define FAT_OPERATION_TRIGGER 0x3 uint32_t read_log_offset; uint32_t read_log_length; uint32_t data_buffer_size; uint32_t data_buffer[0]; } request; struct { uint32_t log_size; uint32_t read_log_length; uint32_t :32; uint32_t :32; uint32_t data_buffer[0]; } response; } params; } mbox_common_manage_fat_t; // mbox_common_read_object_t; typedef struct { uint32_t opcode:8; uint32_t sybsystem:8; uint32_t :16; uint32_t timeout; uint32_t request_length; uint32_t version:8; uint32_t reserved:24; uint32_t desired_read_length:24; uint32_t :8; uint32_t read_offset; #define OBJECT_NAME_LENGTH 26 uint32_t object_name[OBJECT_NAME_LENGTH]; // NULL terminated little endian string uint32_t device_buffer_descriptor_count; mbox_hbd_t device_buffer_descriptor[0]; } mbox_common_read_object_t; typedef struct { uint32_t opcode:8; uint32_t sybsystem:8; uint32_t :16; uint32_t status:8; uint32_t additional_status:8; uint32_t :16; uint32_t response_length; uint32_t actual_response_length; uint32_t actual_read_length; uint32_t :31; uint32_t eof:1; } mbox_common_read_object_rsp_t; // mbox_common_write_object_t; typedef struct { uint32_t opcode:8; uint32_t subsystem:8; uint32_t :16; uint32_t timeout; uint32_t request_length; uint32_t version:8; uint32_t reserved:24; uint32_t desired_write_length:24; uint32_t :6; uint32_t noc:1; uint32_t eof:1; uint32_t write_offset; uint32_t object_name[OBJECT_NAME_LENGTH]; // NULL terminated little endian string uint32_t device_buffer_descriptor_count; mbox_hbd_t device_buffer_descriptor[1]; } mbox_common_write_object_t; // mbox_common_write_object_rsp_t; typedef struct { uint32_t opcode:8; uint32_t sybsystem:8; uint32_t :16; uint32_t status:8; uint32_t additional_status:8; uint32_t :16; uint32_t response_length; uint32_t actual_response_length; uint32_t actual_write_length; uint32_t change_status:8, :24; } mbox_common_write_object_rsp_t; // mbox_common_set_dump_location_t; typedef struct { uint32_t opcode:8; uint32_t subsystem:8; uint32_t :16; uint32_t timeout; uint32_t request_length; uint32_t version:8; uint32_t reserved:24; uint32_t buffer_length:24, :5, fdb:1, blp:1, qry:1; uint32_t buf_addr_low; uint32_t buf_addr_high; } mbox_common_set_dump_location_t; // mbox_common_set_dump_location_rsp_t; typedef struct { uint32_t opcode:8; uint32_t subsystem:8; uint32_t :16; uint32_t timeout; uint32_t request_length; uint32_t version:8; uint32_t reserved:24; uint32_t buffer_length:24, :8; } mbox_common_set_dump_location_rsp_t; // mbox_common_read_object_list_t typedef struct { uint32_t opcode:8; uint32_t sybsystem:8; uint32_t :16; uint32_t timeout; uint32_t request_length; uint32_t version:8; uint32_t reserved:24; uint32_t descriptor_count:16; uint32_t descriptor_offset:16; uint32_t :32; uint32_t object_directory_name[OBJECT_NAME_LENGTH]; uint32_t device_buffer_descriptor_count; mbox_hbd_t device_buffer_descriptor[0]; } mbox_common_read_object_list_t; // mbox_common_read_object_list_rsp_t; typedef struct { uint32_t opcode:8; uint32_t sybsystem:8; uint32_t :16; uint32_t status:8; uint32_t additional_status:8; uint32_t :16; uint32_t response_length; uint32_t actual_response_length; uint32_t actual_descriptor_count:16; uint32_t :16; } mbox_common_read_object_list_rsp_t; // mbox_common_read_object_list_desc_t; typedef struct { uint32_t object_handle:24; uint32_t :5; uint32_t oft:3; #define OFT_NORMAL_OBJECT 0 #define OFT_DIRECTORY_OBJECT 1 #define OFT_LINKED_OBJECT 2 uint32_t object_info; #define OBJECT_BASE_NAME_LENGTH 6 #define REV_NAME_LENGTH 32 uint32_t object_base_name[OBJECT_BASE_NAME_LENGTH]; uint32_t rev_name[REV_NAME_LENGTH]; } mbox_common_read_object_list_desc_t; // mbox_common_delete_object_t typedef struct { uint32_t opcode:8; uint32_t sybsystem:8; uint32_t :16; uint32_t timeout; uint32_t request_length; uint32_t version:8; uint32_t reserved:24; uint32_t :32; uint32_t :32; uint32_t object_name[OBJECT_NAME_LENGTH]; } mbox_common_delete_object_t; // mbox_common_delete_object_rsp_t typedef struct { uint32_t opcode:8; uint32_t sybsystem:8; uint32_t :16; uint32_t status:8; uint32_t additional_status:8; uint32_t :24; uint32_t response_length; uint32_t actual_response_length; } mbox_common_delete_object_rsp_t; #define MBOX_MAX_BUFFER (1024) typedef struct { uint32_t mode:8; uint32_t :8; uint32_t port_mask:16; uint32_t trace_level; uint64_t function_mask; } __attribute__((packed)) ext_fat_mode_t; typedef struct { uint8_t module_str[32]; uint32_t module_id; uint32_t num_modes; ext_fat_mode_t mode_trace_level[1]; } ext_fat_module_t; typedef struct { uint32_t max_log_entries; uint32_t log_entry_size; uint32_t logging_type:8; uint32_t max_logging_functions:8; uint32_t max_logging_ports:8; uint32_t :8; uint32_t supported_modes; #define LOG_MODE_UART_MASK (1U << 0) #define LOG_MODE_RAM_MASK (1U << 1) #define LOG_MODE_NVRAM_MASK (1U << 2) #define LOG_MODE_NWTK_MASK (1U << 3) uint32_t num_modules; ext_fat_module_t debug_module[1]; } ext_fat_config_params_t; // mbox_common_get_ext_fat_capabilities_t typedef struct { mbox_common_t common; union { struct { uint32_t parameter_type; #define EXT_FAT_PARAM_TYPE_DEFAULT 0x0 #define EXT_FAT_PARAM_TYPE_CURRENT 0x1 } request; struct { ext_fat_config_params_t config; } response; } params; } mbox_common_get_ext_fat_capabilities_t; // mbox_common_set_ext_fat_capabilties_t typedef struct { mbox_common_t common; union { struct { ext_fat_config_params_t config; } request; } params; } mbox_common_set_ext_fat_capabilties_t; typedef struct { uint8_t version; uint8_t phy_port; uint16_t fid; uint32_t trace_level; uint64_t module_mask; uint32_t trace_table_index; uint32_t timestamp; uint8_t str_data[16]; uint32_t data[6]; } arm_trace_record_t; // mbox_common_ext_fat_configure_snapshot_t typedef struct { mbox_common_t common; union { struct { uint32_t total_log_entries; } response; } params; } mbox_common_ext_fat_configure_snapshot_t; // mbox_ioctl_common_ext_fat_retrieve_snapshot_t typedef struct { mbox_common_t common; union { struct { #define EXT_FAT_RETRIEVE_MODE_VRAM 0x0 #define EXT_FAT_RETRIEVE_MODE_NVRAM 0x1 uint32_t snapshot_mode ; uint32_t start_index; uint32_t num_log_entries; } request; struct { uint32_t num_log_entries; arm_trace_record_t trace[0]; } response; } params; } mbox_ioctl_common_ext_fat_retrieve_snapshot_t; typedef struct { uint32_t num_returned_bytes; uint32_t num_remaining_bytes; uint8_t table_data[0]; }mbox_ext_fat_read_string_params_t; // ioctl_common_ext_fat_read_string_table_t typedef struct { mbox_common_t common; union { struct { uint32_t byte_offset; uint32_t num_bytes; } request; struct { mbox_ext_fat_read_string_params_t stringtbl; } response; } params; } ioctl_common_ext_fat_read_string_table_t; // mbox_common_iscsi_set_tcp_parameters typedef struct { mbox_common_t common; union { struct { uint32_t request_flags; #define ISCSI_UPDATE_DELAYED_ACK_TIMER 0x01 #define ISCSI_UPDATE_ACK_FREQUENCY 0x04 uint32_t delayed_ack_timer; uint32_t reserved; uint32_t ack_frequency; } request; } params; } mbox_common_iscsi_set_tcp_parameters_t; // mbox_common_iscsi_connection_update typedef struct { mbox_common_t common; union { struct { uint32_t connection_id:16; uint32_t :16; uint32_t request_flags; #define ISCSI_UPDATE_TCP_WINDOW 0x01 uint32_t window_reduction; } request; } params; } mbox_common_iscsi_connection_update_t; // mbox_common_iscsi_get_connection_info typedef struct { mbox_common_t common; union { struct { uint32_t connection_handle; } request; struct { uint32_t source_ip_address[6]; uint32_t dest_ip_address[6]; uint32_t source_port : 16, dest_port : 16; uint32_t tcp_mss; uint32_t interface_handle; uint32_t window_scale_shift_count : 8, reserved : 24; } response; } params; } mbox_common_iscsi_get_connection_info_t; typedef struct { uint32_t opcode:8, subsystem:8, port_number:8, domain:8; uint32_t timeout; uint32_t request_length; uint32_t version:8, :8, pf_number:8, vh_number:8; } sli4_ioctl_request_header_t; typedef struct { uint32_t opcode:8, subsystem:8, :8, domain:8; uint32_t status:8, additional_status:8, :16; uint32_t response_length; uint32_t actual_response_length; } sli4_ioctl_response_header_t; typedef union { sli4_ioctl_request_header_t req; sli4_ioctl_response_header_t res; } sli4_ioctl_header_t; typedef struct { sli4_ioctl_header_t hdr; uint32_t port_status; } sli4_ioctl_common_enable_disable_port_t; typedef struct sli4_sge_s { uint32_t buffer_address_high; uint32_t buffer_address_low; uint32_t data_offset:27, sge_type:4, last:1; uint32_t buffer_length; } sli4_sge_t; /** * be_resources struct */ // 64 bytes per struct typedef struct { uint32_t pf_num:8, vf_domain:8, :16; uint32_t valid_fields; uint32_t session_count:16, icd_count:16; uint16_t cq_count; uint8_t iscsi_mac_address[6]; uint8_t mcc_queue_count; uint8_t bw_percent; uint16_t vlan_id; uint8_t rsvd1[40]; } be_resources_iscsi_v1; typedef struct { uint32_t resource_type:8, :24; be_resources_iscsi_v1 resource_descriptor; // only need iscsi type... } be_resources_v1; typedef struct { sli4_ioctl_header_t hdr; uint32_t resource_descriptor_count; be_resources_v1 be_resources[28]; // Skyhawk will return 28 resource descriptors } sli4_ioctl_common_get_be_configuration_and_resources_t; typedef struct { sli4_ioctl_header_t hdr; uint32_t resource_descriptor_count; be_resources_v1 be_resources[1]; } sli4_ioctl_common_set_be_configuration_and_resources_t; typedef struct sli4_res_common_get_cntl_attributes_s { sli4_ioctl_header_t hdr; uint8_t version_str[32]; uint8_t manufacturer_name[32]; uint32_t supported_modes; uint8_t seeprom_version_lo; uint8_t seeprom_version_hi; uint8_t rsvd0[2]; uint32_t ioctl_data_struct_version; uint32_t ep_fw_data_struct_version; uint8_t ncsi_version_string[12]; uint32_t default_extended_timeout; uint8_t controller_model_number[32]; uint8_t controller_description[64]; uint8_t controller_serial_number[32]; uint8_t ip_version_string[32]; uint8_t firmware_version_string[32]; uint8_t bios_version_string[32]; uint8_t redboot_version_string[32]; uint8_t driver_version_string[32]; uint8_t fw_on_flash_version_string[32]; uint32_t functionalities_supported; uint16_t max_cdblength; uint8_t asic_revision; uint8_t generational_guid[16]; uint8_t hba_port_count; uint16_t default_link_down_timeout; uint8_t iscsi_ver_min_max; uint8_t multifunction_device; uint8_t cache_valid; uint8_t hba_status; uint8_t max_domains_supported; uint8_t phy_port; uint32_t firmware_post_status; uint32_t hba_mtu[8]; uint8_t iSCSI_features; uint8_t asic_generation; uint8_t future_u8[2]; uint32_t future_u32[3]; uint16_t pci_vendor_id; uint16_t pci_device_id; uint16_t pci_sub_vendor_id; uint16_t pci_sub_system_id; uint8_t pci_bus_number; uint8_t pci_device_number; uint8_t pci_function_number; uint8_t interface_type; uint64_t unique_identifier; uint8_t netfilters; uint8_t rsvd1[3]; uint32_t future2_u32[4]; } sli4_res_common_get_cntl_attributes_t; typedef struct sli4_req_common_get_iface_mac_list_s { sli4_ioctl_header_t hdr; uint32_t mac_type:8, permanent_override:8, iface_id:16; uint32_t mac_id; } sli4_req_common_get_iface_mac_list_t; typedef struct sli4_res_common_get_iface_mac_list_s { sli4_ioctl_header_t hdr; uint32_t fd_mac_address0; uint32_t fd_mac_address1; uint32_t macid_mac_address0; uint32_t macid_mac_address1; uint32_t num_tpo_mac:8, num_ppo_mac:8, max_sz_mac_list:8, resv:8; uint32_t po_mac_address[64]; } sli4_res_common_get_iface_mac_list_t; typedef struct sli4_req_common_get_function_config_s { sli4_ioctl_header_t hdr; } sli4_req_common_get_function_config_t; typedef struct sli4_res_common_get_function_config_s { sli4_ioctl_header_t hdr; uint32_t desc_count; uint32_t desc[0]; } sli4_res_common_get_function_config_t; typedef struct sli4_req_common_get_profile_config_s { sli4_ioctl_header_t hdr; uint32_t profile_id:8, typ:2, census_mode:1, :21; } sli4_req_common_get_profile_config_t; typedef struct sli4_res_common_get_profile_config_s { sli4_ioctl_header_t hdr; uint32_t desc_count; uint32_t desc[0]; } sli4_res_common_get_profile_config_t; typedef struct sli4_req_common_set_profile_config_s { sli4_ioctl_header_t hdr; uint32_t profile_id:8, :23, isap:1; uint32_t desc_count; uint32_t desc[0]; } sli4_req_common_set_profile_config_t; typedef struct sli4_res_common_set_profile_config_s { sli4_ioctl_header_t hdr; } sli4_res_common_set_profile_config_t; #define MAX_DESCRIPTION 128*4 typedef struct sli4_profile_descriptor_s { uint32_t profile_id:8, :8, profile_index:8, :8; uint8_t profile_description_string[MAX_DESCRIPTION]; } sli4_profile_descriptor_t; typedef struct sli4_req_common_get_profile_list_s { sli4_ioctl_header_t hdr; uint32_t start_profile_index:8, :24; } sli4_req_common_get_profile_list_t; typedef struct sli4_res_common_get_profile_list_s { sli4_ioctl_header_t hdr; uint32_t desc_count; sli4_profile_descriptor_t desc[0]; } sli4_res_common_get_profile_list_t; typedef struct sli4_req_common_get_active_profile_s { sli4_ioctl_header_t hdr; } sli4_req_common_get_active_profile_t; typedef struct sli4_res_common_get_active_profile_s { sli4_ioctl_header_t hdr; uint32_t active_profile_id:8, :8, next_profile_id:8, :8; } sli4_res_common_get_active_profile_t; typedef struct sli4_req_common_set_active_profile_s { sli4_ioctl_header_t hdr; uint32_t active_profile_id:8, :23, fd:1; } sli4_req_common_set_active_profile_t; typedef struct sli4_res_common_set_active_profile_s { sli4_ioctl_header_t hdr; } sli4_res_common_set_active_profile_t; typedef struct { uint32_t type:8, length:8, :6, pool:1, lldv:1, :1, macv:1, vlv:1, :1, qun:1, del:1, imm:1, nosv:1; uint32_t :16, pf_number:10, :6; uint32_t session_count:16, icd_count:16; uint16_t cq_count; uint8_t mac_address[6]; uint32_t other[17]; } sli4_iscsi_resource_descriptor_v1_t; typedef struct { uint32_t type:8, length:8, :6, pool:1, lldv:1, icfv:1, macv:1, vlv:1, vft:1, qun:1, del:1, imm:1, nosv:1; uint32_t vf_number:8, :8, pf_number:10, :6; uint16_t unicast_count; uint8_t mac_address[6]; uint32_t other[18]; } sli4_nic_resource_descriptor_v1_t; typedef struct { uint32_t type:8, :15, lldv:1, icfv:1, macv:1, vlv:1, vft:1, qun:1, del:1, imm:1, nosv:1; uint32_t vf_number:8, :8, pf_number:10, :6; uint16_t unicast_count; uint8_t mac_address[6]; uint32_t other[14]; } sli4_nic_resource_descriptor_v0_t; typedef struct { uint32_t type:8, :18, vlv:1, vft:1, qun:1, del:1, imm:1, nosv:1; uint32_t vf_number:8, :8, pf_number:10, :6; uint16_t counts[8]; uint8_t wwnn[8]; uint8_t wwpn[8]; uint8_t mac_addr[6]; uint16_t rsvd1; uint32_t other[6]; } sli4_fcfcoe_resource_descriptor_v0_t; typedef struct { sli4_ioctl_header_t hdr; uint32_t cmd_buf_length; uint32_t resp_buf_length; uint32_t cmd_buf_addr_low; uint32_t cmd_buf_addr_high; uint32_t resp_buf_addr_low; uint32_t resp_buf_addr_high; } sli4_req_dmtf_exec_clp_cmd_t; typedef struct { sli4_ioctl_header_t hdr; uint32_t rsvd1; uint32_t resp_length; uint32_t rsvd2[4]; uint32_t clp_status; uint32_t clp_detailed_status; } sli4_res_dmtf_exec_clp_cmd_t; /* Link Config Descriptor for link config functions */ typedef struct { uint32_t link_config_id:8, :24; uint32_t config_description[8]; } sli4_link_config_descriptor_t; #define MAX_LINK_CONFIG_DESCRIPTORS 10 typedef struct { sli4_ioctl_header_t hdr; } sli4_req_get_reconfig_link_info_t; typedef struct { sli4_ioctl_header_t hdr; uint32_t active_link_config_id:8, :8, next_link_config_id:8, :8; uint32_t link_config_desc_count; sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS]; } sli4_res_get_reconfig_link_info_t; typedef struct { sli4_ioctl_header_t hdr; uint32_t next_link_config_id:8, :23, factory_default:1; } sli4_req_set_reconfig_link_info_t; typedef struct { sli4_ioctl_header_t hdr; } sli4_res_set_reconfig_link_info_t; #endif // __ELXU_SLI4_H__