/*******************************************************************************

NAME            pchLpcDiag.h
SUMMARY         header file for Ibex Peak LPC interface function diagnostics
VERSION         %version: 1 %
UPDATE DATE     %date_modified: Jun 5 15:00 2009 %
PROGRAMMER      %created_by:    Jim Tu %

        Copyright 2009 Quanta Corporation. All Rights Reserved.

DESCRIPTION:
        This file has code to test Ibex Peak LPC interface

NOTES:

REFERENCE:

*******************************************************************************/

#ifndef __IBX_DEFINE_H__
#define __IBX_DEFINE_H__


#define INTEL_IBX_PCI_BRIDGE_DEVICE_ID	0x244E
#define INTEL_IBX_NIC_82577_DEVICE_ID	0x3B41

#define INTEL_IBX_LPC_DEVICE_ID		0x3B14

#define INTEL_IBX_SATA_AHCI_DEVICE_ID	0x3B22
#define INTEL_IBX_THERMAL_DEVICE_ID		0x3B32
#define INTEL_IBX_UHCI_1_DEVICE_ID		0x3B36
#define INTEL_IBX_UHCI_2_DEVICE_ID		0x3B37
#define INTEL_IBX_UHCI_3_DEVICE_ID		0x3B38
#define INTEL_IBX_UHCI_4_DEVICE_ID		0x3B39
#define INTEL_IBX_UHCI_5_DEVICE_ID		0x3B3B
#define INTEL_IBX_UHCI_6_DEVICE_ID		0x3B3E
#define INTEL_IBX_UHCI_7_DEVICE_ID		0x3B3A
#define INTEL_IBX_UHCI_8_DEVICE_ID		0x3B40
#define INTEL_IBX_UHCI_9_DEVICE_ID		0x3B3F
#define INTEL_IBX_EHCI_1_DEVICE_ID		0x3B34
#define INTEL_IBX_EHCI_2_DEVICE_ID		0x3B3C
#define INTEL_IBX_PCIE_PORT_1_DEVICE_ID 0x3B42
#define INTEL_IBX_PCIE_PORT_2_DEVICE_ID 0x3B44
#define INTEL_IBX_PCIE_PORT_3_DEVICE_ID 0x3B46
#define INTEL_IBX_PCIE_PORT_4_DEVICE_ID 0x3B48
#define INTEL_IBX_PCIE_PORT_5_DEVICE_ID 0x3B4A
#define INTEL_IBX_PCIE_PORT_6_DEVICE_ID 0x3B4C
#define INTEL_IBX_PCIE_PORT_7_DEVICE_ID 0x3B4E
#define INTEL_IBX_PCIE_PORT_8_DEVICE_ID 0x3B50
#define INTEL_IBX_VECI_DEVICE_ID		0x3B53
#define INTEL_IBX_HECI_1_DEVICE_ID		0x3B64
#define INTEL_IBX_HECI_2_DEVICE_ID		0x3B65

/* PCIE Register */
#define IBX_RCBA_OFFSET					0xF0
#define IBX_DMI_LSTS_OFFSET				0x01A9
#define IBX_PCIE_LSTS_OFFSET			0x52

#define IBX_RCBA_LENGTH					0x35B4

#define IBX_PCIE_X4_LINK_WIDTH			0x41
#define IBX_PCIE_X2_LINK_WIDTH			0x21
#define IBX_PCIE_X1_LINK_WIDTH			0x11

/* power management */
#define IBX_NIC_82577_PMCS_OFFSET		0xCC
#define IBX_SATA_PMCS_OFFSET			0x74
#define IBX_EHCI_PMCS_OFFSET			0x54
#define IBX_THERMAL_PMCS_OFFSET			0x54
#define IBX_PCIE_PORT_PMCS_OFFSET		0xA4
#define IBX_VECI_PMCS_OFFSET			0x54
#define IBX_HECI_PMCS_OFFSET			0x54

#define	IBX_PMCS_POWER_STATE_BITS		0x03

#define IBX_PMCS_D0_STATE				0xFC
#define IBX_PMCS_D3_STATE				0x03

/* RTC */
#define IBX_RTC_1_INDEX_IOPORT			0x70
#define IBX_RTC_1_TARGET_IOPORT			0x71
#define IBX_RTC_2_INDEX_IOPORT			0x72
#define IBX_RTC_2_TARGET_IOPORT			0x73

#define IBX_RTC_SECONDS_INDEX			0x00
#define IBX_RTC_SECONDS_ALARM_INDEX		0x01
#define IBX_RTC_MINUTES_INDEX			0x02
#define IBX_RTC_MINUTES_ALARM_INDEX		0x03
#define IBX_RTC_HOURS_INDEX				0x04
#define IBX_RTC_HOURS_ALARM_INDEX		0x05
#define IBX_RTC_DAY_OF_WEEK_INDEX		0x06
#define IBX_RTC_DAY_OF_MONTH_INDEX		0x07
#define IBX_RTC_MONTH_INDEX				0x08
#define IBX_RTC_YEAR_INDEX				0x09
#define IBX_RTC_REG_A_INDEX				0x0A
#define IBX_RTC_REG_B_INDEX				0x0B
#define IBX_RTC_REG_C_INDEX				0x0C
#define IBX_RTC_REG_D_INDEX				0x0D

#define IBX_RTC_REG_A_UIP_BIT			0x80
#define IBX_RTC_REG_B_SET_BIT			0x80
#define IBX_RTC_REG_B_DM_BIT			0x04
#define IBX_RTC_REG_B_HF_BIT			0x02

#define SYSCLKRATE                      100

#define RTC_INIT_SIGNATURE              ('R' << 24 | 'T' << 16 | 'C' << 8 | 'I')

#define RTC_DM_BIT						0x04

#define RTC_BCD_MODE					0
#define RTC_BINARY_MODE					1

//#ifndef __RTC_TIME__
//#define __RTC_TIME__
//struct rtc_time {
//	INT32 tm_sec;
//	INT32 tm_min;
//	INT32 tm_hour;
//	INT32 tm_mday;
//	INT32 tm_mon;
//	INT32 tm_year;
//	INT32 tm_wday;
//	INT32 tm_yday;
//	INT32 tm_isdst;
//};
//#endif //__RTC_TIME__

//#ifndef _TIMESPEC_DECLARED
//#define _TIMESPEC_DECLARED
//struct timespec {
//	time_t	tv_sec;		/* seconds */
//	long	tv_nsec;	/* and nanoseconds */
//};
//#endif

/* 8259 Interrupt/GPIO */
#define IBX_8259_MASTER_FIRST_PORT			0x20
#define IBX_8259_MASTER_SECOND_PORT			0x21
#define IBX_8259_SLAVE_FIRST_PORT			0xA0
#define IBX_8259_SLAVE_SECOND_PORT			0xA1
#define IBX_8259_MASTER_PIC_TRIGGERED_PORT	0x4D0
#define IBX_8259_SLAVE_PIC_TRIGGERED_PORT	0x4D1

//Master port is for ICW1, OCW2, OCW3
//Slave port is for ICW2, ICW3, ICW4, OCW1

#define IBX_8259_ICW1			0x01
#define IBX_8259_ICW2			0x
#define IBX_8259_ICW3_MASTER	0x04
#define IBX_8259_ICW3_SLAVE		0x02
#define IBX_8259_ICW4			0x01
#define IBX_8259_OCW1			0x
#define IBX_8259_OCW2			0x
#define IBX_8259_OCW3			0x

#define IBX_GPIO_BAR_OFFSET		0x48
#define IBX_GPIO_LVL_OFFSET		0x0C

#define IBX_GPIO_BOARD_ID_SKU0	0x04
#define IBX_GPIO_BOARD_ID_SKU1	0x08
#define IBX_GPIO_BOARD_ID_SKU2	0x10
#define IBX_GPIO_BOARD_ID_SKU3	0x20

#define IBX_GPIO_BOARDID		0x08

#endif	//__IBX_LPC_DIAG_H__