/*******************************************************************************

NAME			$RCSfile: memLib.h,v $
SUMMARY			Memory Diagnostics Header File
VERSION			$Revision: 1.8 $
UPDATE DATE		$Date: 2010/05/28 06:30:56 $
PROGRAMMER		$Author: small $

		Copyright 2009 LSI Corporation. All Rights Reserved.

DESCRIPTION:

REFERENCE:

*******************************************************************************/
#ifndef __INCmemLib
#define __INCmemLib
/***  INCLUDES  ***/
#include "commTypes.h"

/***  CONSTANT DEFINATIONS  ***/
#define		MEM_CONFIG_MAX_CHAN						3
#define		MEM_CONFIG_MAX_DIMM						3
#define		MEM_CACHE_LINE_SIZE						0x40
#define		MEM_CHAN_INTL_SIZE						0x1000

#define		MEM_TEST_DEFAULT_LOOP					1
#define		MEM_TOTAL_PROGRESS_UINT					100
#define		MEM_COMPLETE_PROGRESS_UINT				0
#define		MEM_HALF_PROGRESS_UINT					(MEM_TOTAL_PROGRESS_UINT / 2)
#define		MEM_QUANTER_PROGRESS_UINT				(MEM_TOTAL_PROGRESS_UINT / 4)
#define		MEM_FIFTH_PROGRESS_UINT					(MEM_TOTAL_PROGRESS_UINT / 5)
#define		MEM_TENTH_PROGRESS_UINT					(MEM_TOTAL_PROGRESS_UINT / 10)
#define		MEM_WORD_PATTERN_PROGRESS_UINT			16
#define		MEM_DMA_OPER_PROGRESS_UINT				50

#define		MEM_JF_CORE_DID							0x3728
#define		MEM_JF_CORE_REG_TOLM_OFFSET				0xD0
#define		MEM_JF_CORE_REG_TOHML_OFFSET			0xD4
#define		MEM_JF_CORE_REG_TOHMH_OFFSET			0xD8
#define		MEM_JF_CORE_REG_TOHMH_START				0x100000000
#define		MEM_JF_CORE_REG_TOM_MASK				0xFC000000
#define		MEM_JF_CORE_REG_TSEGCTRL_OFFSET			0xA8
#define		MEM_JF_CORE_REG_TSEG_ENABLE				0x00000001
#define		MEM_JF_CORE_REG_TSEG_ADDR_MASK			0xFFF00000
#define		MEM_JF_CORE_REG_TSEG_SIZE_MASK			0x0000000E
#define		MEM_JF_CORE_REG_TSEG_SIZE_BASE			0x00080000

/* How to caculate the ID, refer to Intel_418294 Page 409
 * example:
 * Dev 3 func 2 will be mapping to 0x8000000 and the Dev is occupied 5 bit, func is 3 bit
 * then
 *  dev  fun
 * |  3  | 2 |
 *  00011 010 = 0x18 + 0x02 = EM_IMC_CTL_DEVICE_ID + MEM_IMC_CTL_RAS_FUNC
 * Jay  */
#define		MEM_IMC_DOMAIN_ID						0x0
#define		MEM_IMC_BUS_ID							0xFF
#define		MEM_IMC_CTL_DEVICE_ID					0x18	/* Device 3 */
#define		MEM_IMC_CTL_RAS_FUNC					0x02	/* Function 2*/
#define		MEM_IMC_CHAN0_DEVICE_ID					0x20	/* Device 4 */
#define		MEM_IMC_CHAN1_DEVICE_ID					0x28	/* Device 5 */
#define		MEM_IMC_CHAN2_DEVICE_ID					0x30	/* Device 6 */
#define		MEM_IMC_CHAN_ADDR_FUNC					0x01

#define		MEM_IMC_CTL_MC_CONTROL					0x48
#define		MEM_IMC_CTL_MC_CHANNEL_MAPPER			0x60
#define		MEM_IMC_CHAN_ADDR_MC_DOD_CH_0			0x48
#define		MEM_IMC_CHAN_ADDR_MC_DOD_CH_1			0x4C
#define		MEM_IMC_CHAN_ADDR_MC_DOD_CH_2			0x50
#define		MEM_IMC_COR_ECC_CNT_0					0x80
#define		MEM_IMC_COR_ECC_CNT_1					0x88
#define		MEM_IMC_COR_ECC_CNT_2					0x90

#define		MEM_DIAG_CORRECTABLE_ECC				0
#define		MEM_DIAG_NONCORRECTABLE_ECC				1
#define		MEM_DIAG_ECC_CYCLE						3
#define		MEM_MC_CHANNEL_ADDR_MATCH				0xF0
#define		MEM_MC_CHANNEL_ECC_ERROR_MASK			0xF8
#define		MEM_MC_CHANNEL_ECC_ERROR_INJECT			0xFC
#define		MEM_MC_ENABLE_ECC_ERROR_INJECT			0x000E
#define		MEM_DIAG_ECC_MAX_DIMM_NUM				3
#define		MEM_DIAG_ECC_DIMM_BIT_SHIFT				4
#define		MEM_DIAG_ECC_THREE_DIMM_BIT_SHIFT		3
#define		MEM_DIAG_ECC_RANK_BIT_SHIFT				2
#define		MEM_DIAG_ECC_ADDR_MASK					0x000000E0
#define		MEM_DIAG_ECC_ECC_INJECT_UPPER			0x0000000C	//0x0000000A //the defined is corrected by Jay, refer to 418294 page 505
#define		MEM_DIAG_ECC_ECC_INJECT_LOWER			0x0000000A	//0x0000000C //the defined is corrected by Jay, refer to 418294 page 505
#define		MEM_RAM_IOREMAP_MAX_SIZE				(64 * MB)

/***  MACRO DEFINATIONS  ***/
#define M_INIT_TEST_BASE(startAddr) do { \
	if((startAddr < gMemDiagStartAddr)	\
		|| (startAddr > (gMemDiagStartAddr + gMemDiagRegionSize))) \
		startAddr = gMemDiagStartAddr;	\
} while (0)

#define M_INIT_TEST_REGION(startAddr, sizeTest) do { \
	if((sizeTest == 0) || (sizeTest > gMemDiagRegionSize)	\
		|| ((startAddr + sizeTest) > (gMemDiagStartAddr + gMemDiagRegionSize)))	\
		sizeTest = (gMemDiagStartAddr + gMemDiagRegionSize) - startAddr;	\
} while (0)

#define M_INIT_TEST_LOOP(loopTest) do { \
	if(loopTest == 0) loopTest = MEM_TEST_DEFAULT_LOOP;	\
} while (0)


#define M_MEM_RESET_PROGRESS(cur, rpt) do { \
	cur =0 ;	\
	rpt = cur;	\
} while (0)

#define M_SET_REPORT_STRING(item, str) do { \
	if(item == MEM_DIAG_ITEM_CODE_MARCHC) {	\
		str = "Memory MarchC Test";	\
    } else if (item == MEM_DIAG_ITEM_CODE_EXTENDPATTERNS) {	\
		str = "Memory Word Pattern Test";	\
    } else if (item == MEM_DIAG_ITEM_CODE_ADMAOPERATION) {	\
		str = "Memory DMA Operation Test";	\
	} else {	\
		str = "Unknown Memory Test";	\
	}	\
} while (0)

#define M_MEM_REPORT_PROGRESS(str, cur, rpt, incr) do { \
	cur+=incr;	\
    if ((cur > 0) && (cur > rpt)) {	\
		commPostProgress(str, cur, MEM_TOTAL_PROGRESS_UINT);	\
		rpt = cur;	\
	} else if ((incr == 0) && (cur != MEM_TOTAL_PROGRESS_UINT)){	\
		commPostProgress(str, MEM_TOTAL_PROGRESS_UINT, MEM_TOTAL_PROGRESS_UINT);	\
	}	\
} while (0)

/***  TYPE DEFINATIONS  ***/
typedef struct memoryDimmConfiguration
{
	UINT8			numRank;
	UINT64			sizeRank;
} MEM_DIMM_CFG;

typedef struct memoryChannelConfiguration
{
	MEM_DIMM_CFG	dimmCfg[MEM_CONFIG_MAX_DIMM];
	BOOLEAN			enableChan;
	UINT8			totalDimm;
} MEM_CHAN_CFG;

typedef struct memoryAddr
{
	UINT8	idxChan;
	UINT8	idxRank;
	UINT8	idxDimm;
	UINT8	totalDimm;
} MEM_ADDR;

typedef struct memoryDiagCommand
{
	UINT8  	testItemCode;	//test item code
	UINT64 	testAddr;		//the head address of the memory region
	UINT64 	testSize;		//the number of bytes to read/verify/write
	UINT64 	verifyPattern;	//the pattern asked to be verified
	UINT64 	writePattern;	//the pattern asked to be written
	BOOLEAN testForward;	//the marching direction
	UINT32 	*curProgress;
	UINT32 	*rptProgress;
	UINT32 	unitProgress;
	
} MEM_CMD;

/***  EXTERNAL REFERENCES ***/
UINT64 memGetMemConfig(VOID);
VOID memSetDiagStartAddr( UINT64 start_addr);
#endif	//__INCmemLib