/******************************************************************************* NAME $RCSfile: plxDiag.h,v $ SUMMARY Header file of PLX PCI-E switch diagnostics for Pikes Peak VERSION $Revision: 1.10 $ UPDATE DATE $Date: 2009/12/16 03:49:00 $ PROGRAMMER $Author: luap $ Copyright 2009 LSI Corporation. All Rights Reserved. DESCRIPTION: REFERENCE: *******************************************************************************/ #ifndef INCplxDiag #define INCplxDiag #include #include /* Configuration space registers */ #define PLX_PCIEDSTS 0x72 /* PCI Express Device Status */ #define PLX_PCIELCAP 0x74 /* PCI Express Link Capabilities */ #define PLX_PCIELSTS 0x7a /* PCI Express Link Status */ #define PIKES_PEAK_PLX_PORT_NUM 5 #define PLX_UPSTREAM_LANE_WIDTH 16 #define PLX_DOWNSTREAM_LANE_WIDTH 8 #define PLX_PORT_USED 0x01 typedef struct { uint8_t flag; uint8_t portNum; uint8_t laneWidth; uint8_t linkSpeed; struct pci_dev *pdev; } PLX_PORT; /*XXX: There are 12 physical ports for PEX8648/PEX8649 * Somehow PEX8649 has max port index to 23 */ #define MAX_PLX_PORT 24 typedef struct { uint16_t deviceID; uint8_t ntb; PLX_PORT port[MAX_PLX_PORT]; } PLX_PCIE_SWT; #define PLX_MSG_SHIFT 18 /* 256K */ #define PLX_MSG_SIZE (1 << 18) #define PLX_MSG_BODY_SIZE (PLX_MSG_SIZE - sizeof(uint32_t)) #define PLX_MSG_NO_SIGNATURE 0x00000000 #define PLX_MSG_REQ_SIGNATURE 0xaaaaaaaa #define PLX_MSG_RSP_SIGNATURE 0x55555555 typedef struct { volatile uint32_t signature; volatile uint8_t body[PLX_MSG_BODY_SIZE]; } PLX_MSG; typedef struct { int rxDone; PLX_MSG *txMsg; PLX_MSG *rxMsg; } PLX_NT_DIAG_CB; /******************************************************* * NT Bridge Settings *******************************************************/ #define PLX_NT_BACK_TO_BACK #define PLX_NT_MAP_BASE 0x800000000ULL /* 32GB */ //#define PLX_NT_WINDOW_SIZE 0x20000000ULL /* 512 MB */ #define PLX_NT_WINDOW_SIZE 0x10000000ULL /* 256 MB */ /* Modified by Luap 20091216 */ //#define PLX_NT_TRANS_ADDR 0x20000000ULL /* 512 MB */ #define PLX_NT_TRANS_ADDR 0x60000000ULL /* 1536 MB */ /* Modified by Luap 20091216 */ #define PLX_NT_BUFFER_SIZE (1024*1024) /* 1MB */ #define PCISTS_MDPED 0x0100 /* Master Data Parity Error Detected */ #define PCISTS_SSE 0x4000 /* Signalled System Error */ #define PCISTS_DPE 0x8000 /* Detected Parity Error */ #define PCISTS_ERROR_MASK (PCISTS_MDPED | PCISTS_SSE | PCISTS_DPE) #define PCIESTS_CED 0x0001 /* Correctable Error Detected */ #define PCIESTS_NFED 0x0002 /* Non-Fatal Error Detected */ #define PCIESTS_FED 0x0004 /* Fatal Error Detected */ #define PCIESTS_URD 0x0008 /* Unsupported Request Detected */ #define PCIESTS_ERROR_MASK (PCIESTS_CED | PCIESTS_NFED | PCIESTS_FED | PCIESTS_URD) #define AERUES_DLPERR (1 << 4) /* Data Link Protocol Error Status */ #define AERUES_SDOENERR (1 << 5) /* Surprise Down Error Status */ #define AERUES_POISONED (1 << 12) /* Poisoned TLP Status */ #define AERUES_FCPERR (1 << 13) /* Flow Control Protocol Error Status */ #define AERUES_CTS (1 << 14) /* Completion Timeout Status */ #define AERUES_CAS (1 << 15) /* Completion Abort Status */ #define AERUES_UECOMP (1 << 16) /* Unexpected Completion Status */ #define AERUES_RCVOVR (1 << 17) /* Receiver Overflow Status */ #define AERUES_MALFORMED (1 << 18) /* Malformed TLP Status */ #define AERUES_ECRC (1 << 19) /* ECRC Status */ #define AERUES_UR (1 << 20) /* UR Status */ #define AERUES_ACSVES (1 << 21) /* ACS Violation Error Status */ #define AERCES_RCVERR (1 << 0) /* Receiver Error Status */ #define AERCES_BADTLP (1 << 6) /* Bad TLP Status */ #define AERCES_BADDLLP (1 << 7) /* Bad DLLP Status */ #define AERCES_RPLYROVR (1 << 8) /* Reply Number Rollover Status */ #define AERCES_RPLYTO (1 << 12) /* Replay Timer Time-Out Status */ #define AERCES_ADVISORYNF (1 << 13) /* Advisory Non-Fatal Error Status */ #endif /* INCplxDiag */