#ifndef __QE8_STRESS_H__ #define __QE8_STRESS_H__ #define QE8_IPC_TIMEOUT 3000 /* 3000 ms */ #define SIG_IO_TEST_START SIGUSR1 #define SIG_IO_TEST_STOP SIGUSR2 #define SYSSTRESS_CPI_CMD_IO 250 #define ROLE_UUT 0 #define ROLE_FIXTURE 1 #define QE8_INIT_ROUTINE 0 #define QE8_CLEANUP_ROUTINE 1 #define QE8_TGT_ROLE 0 #define QE8_INI_ROLE 1 #define QE8_TGT_INI_NUM 2 #define QE8_CONTROLLER_NUM 2 #define _MB (1 << 20) #define QE8_DMA_SIZE (4 * _MB) // 4MB DMA for QE8 board stress #define NUM_BLKS 4 /********************* ****** Macros ******* ********************/ /* Get the port index of the board stress stage by * * giving the port index of the diag stage. */ #define M_QE8_PORT_IDX_D2B(idx) \ ((idx + QE8_SHIFT_ENTRY) % QE8_BS_NUM_PORT) #define QE8_DAUGHTER_ONLY 2 #define QE8_BORAD_N_DAUGHTER 8 #define M_QE8_DAUGHTER_EXIST(qe8_count) \ (qe8_count == QE8_BORAD_N_DAUGHTER ? true : false) /************************************************ * QE8_PORT_1 -> port 0 of the on board QE8 * * QE8_PORT_2 -> port 1 of the on board QE8 * * QE8_PORT_3 -> port 2 of the on board QE8 * * QE8_PORT_4 -> port 3 of the on board QE8 * * QE8_PORT_5 -> port 0 of the QE8 HIC * * QE8_PORT_6 -> port 1 of the QE8 HIC * * QE8_PORT_7 -> port 2 of the QE8 HIC * * QE8_PORT_8 -> port 3 of the QE8 HIC * ***********************************************/ #define QE8_PORT_1 (1 << 0) #define QE8_PORT_2 (1 << 1) #define QE8_PORT_3 (1 << 2) #define QE8_PORT_4 (1 << 3) #define QE8_PORT_5 (1 << 4) #define QE8_PORT_6 (1 << 5) #define QE8_PORT_7 (1 << 6) #define QE8_PORT_8 (1 << 7) #define QE8_BS_NUM_PORT 8 #define QE8_BS_PORT_SPEED_2G 2 #define QE8_BS_PORT_SPEED_4G 3 #define QE8_BS_PORT_SPEED_8G 4 #define QE8_REMOTE_SOC_CH 2 #define QE8_LOCAL_SOC_CH 3 #define QE8_TX_4G_PISO 0x01 /* The PSIO mode */ #define QE8_TX_4G_PE_IMP 0x01 /* The impendance of the pre-emphasis */ #define QE8_TX_4G_SWING 0x0000 /* Swing */ #define QE8_TX_4G_DEN 0x1E9F /* Den */ #define QE8_TX_4G_PE2_SEL 0x00 /* edge-rage control */ #define QE8_TX_4G_PE2_CTRL 0x00 /* PE2 control of the pre-emphasis */ #define QE8_TX_4G_PE1_CTRL 0x0B /* PE1 control of the pre-emphasis */ /* The 8G signal strength for QE8 front-end ports * * (port index 0-1 in diag stage). */ #define QE8_FE_TX_8G_PISO 0x00 /* The PSIO mode */ #define QE8_FE_TX_8G_PE_IMP 0x01 /* The impendance of the pre-emphasis */ #define QE8_FE_TX_8G_SWING 0x0e1f /* Swing */ #define QE8_FE_TX_8G_DEN 0x11e0 /* Den */ #define QE8_FE_TX_8G_PE2_SEL 0x00 /* edge-rage control */ #define QE8_FE_TX_8G_PE2_CTRL 0x00 /* PE2 control of the pre-emphasis */ #define QE8_FE_TX_8G_PE1_CTRL 0x00 /* PE1 control of the pre-emphasis */ /* The 8G signal strength for QE8 daughter ports * * (port index 4-5 in diag stage). */ #define QE8_DT_TX_8G_PISO 0x01 /* The PSIO mode */ #define QE8_DT_TX_8G_PE_IMP 0x01 /* The impendance of the pre-emphasis */ #define QE8_DT_TX_8G_SWING 0x101F /* Swing */ #define QE8_DT_TX_8G_DEN 0x0FE0 /* Den */ #define QE8_DT_TX_8G_PE2_SEL 0x00 /* edge-rage control */ #define QE8_DT_TX_8G_PE2_CTRL 0x00 /* PE2 control of the pre-emphasis */ #define QE8_DT_TX_8G_PE1_CTRL 0x00 /* PE1 control of the pre-emphasis */ #define QE8_SHIFT_ENTRY 2 #define QE8_CFG_PHY_SPEED_NUM 2 #define QE8_EC_DF_MSK 0xFF000000 /* Mask of Discard Frame Error Count */ #define QE8_EC_BRC_MSK 0x00FF0000 /* Mask of Bad Rx Char Error Count */ #define QE8_EC_LS_MSK 0x0000FF00 /* Mask of Loss of Sync Error Count */ #define QE8_EC_PE_MSK 0x000000FF /* Mask of Protocol Error Count */ #define QE8_EC_DF_SB 24 /* Shift bits of Discard Frame EC */ #define QE8_EC_BRC_SB 16 /* Shift bits of Bad Rx Char EC */ #define QE8_EC_LS_SB 8 /* Shift bits of Loss of Sync EC */ #define QE8_EC_PE_SB 0 /* Shift bits of Protocol Error EC */ /* Note: QE8_DIAG is mutual exclusive with * * QE8_TGT_BS and QE8_INI_BS */ #define QE8_DIAG (1 << 0) // QE8 diag stage #define QE8_TGT_BS (1 << 1) // QE8 target board stress #define QE8_INI_BS (1 << 2) // QE8 initiator board stress #define FC_ERR_CNT_THSH 1 /* The threshold error count of FC. */ #define agbool bool #define agtrue true #define agfalse false typedef unsigned char bit8; typedef unsigned short bit16; typedef unsigned int bit32; typedef char S08; typedef short S16; typedef int S32; typedef long S32_64; typedef long long S64; typedef unsigned char U08; typedef unsigned short U16; typedef unsigned int U32; typedef unsigned long U32_64; typedef unsigned long long U64; typedef uint32_t (*QE8_BS_REQ_OPS_FNPTR)(unsigned int, unsigned int); typedef enum { QE8_SET_PORT_SPEED = 0, QE8_DUMP_ERR_CNT, } QE8_OPS; #ifndef hpRoot_t typedef struct hpRoot_s { void *fcData; void *osData; } hpRoot_t; #endif extern unsigned int g_qe8_stage; extern unsigned int sysCtrlRole; extern unsigned int QE8BSTgtSetPortSpeed(unsigned int port_idx, unsigned int port_speed); extern unsigned int QE8BSIniSetPortSpeed(unsigned int port_idx, unsigned int port_speed); extern unsigned int QE8BSTgtDumpErrCnt(unsigned int port_idx, unsigned int num_port); extern unsigned int QE8BSIniDumpErrCnt(unsigned int port_idx, unsigned int num_port); extern void qe8DumpErrorCount(bool); extern unsigned int g_local_qe8_cnt; extern bool QE8GetHpRoot(unsigned int port_idx, hpRoot_t **hp_rootPP); extern bool QE8IniGetHpRoot(unsigned int port_idx, hpRoot_t **hp_rootPP); extern unsigned int osChipRegRead ( hpRoot_t * hpRoot, unsigned int chipIOOffset ); typedef struct s_fc_stress_Param { unsigned int channel[8]; unsigned int times; unsigned int BS; unsigned int speed; unsigned int pattern; unsigned int SOE; unsigned int dv; }fc_stress_Param_t; typedef struct s_proc_fc_status { unsigned int speed; #if 0 unsigned int link_status1; unsigned int link_status2; #endif unsigned int idx; }proc_fc_status_t; typedef struct hpFCPortStart_s { unsigned int sysIntsActive; unsigned int hpTopology; unsigned int RetryCount; } hpFCPortStart_t; typedef struct _ag_dma_addr { caddr_t dmaVirtAddr; dma_addr_t dmaPhysAddr; U32 memSize; bit32 type; } ag_dma_addr_t; typedef struct tiRoot { void *osData; void *tdData; } tiRoot_t; //**************************** #define MAX_LL_LAYER_MEM_DESCRIPTORS 64 typedef struct tiMem { void *virtPtr; void *osHandle; bit32 physAddrUpper; bit32 physAddrLower; bit32 totalLength; bit32 numElements; bit32 singleElementLength; bit32 alignment; bit32 type; bit32 reserved; } tiMem_t; typedef struct tiLoLevelMem { bit32 count; tiMem_t mem[MAX_LL_LAYER_MEM_DESCRIPTORS]; } tiLoLevelMem_t; typedef struct tiLoLevelOption { bit32 usecsPerTick; bit32 numOfQueuesPerPort; bit32 mutexLockUsage; bit32 pciFunctionNumber; bit32 maxPortContext; agbool encryption; bit32 maxInterruptVectors; agbool multipleOutboundRequests; } tiLoLevelOption_t; typedef struct tiInitiatorMem { bit32 count; tiMem_t tdCachedMem[6]; } tiInitiatorMem_t; typedef struct tiInitiatorOption { bit32 usecsPerTick; bit32 pageSize; tiMem_t dynamicDmaMem; tiMem_t dynamicCachedMem; bit32 ioRequestBodySize; } tiInitiatorOption_t; typedef struct tiTargetMem { bit32 count; tiMem_t tdMem[10]; } tiTargetMem_t; typedef struct tiTargetOption { bit32 usecsPerTick; bit32 pageSize; bit32 numLgns; bit32 numSessions; bit32 numXchgs; tiMem_t dynamicDmaMem; tiMem_t dynamicCachedMem; } tiTargetOption_t; //############################# typedef struct tiLoLevelResource { tiLoLevelOption_t loLevelOption; tiLoLevelMem_t loLevelMem; } tiLoLevelResource_t; typedef struct tiInitiatorResource { tiInitiatorOption_t initiatorOption; tiInitiatorMem_t initiatorMem; } tiInitiatorResource_t; typedef struct { tiTargetOption_t targetOption; tiTargetMem_t targetMem; } tiTargetResource_t; typedef struct tiTdSharedMem { tiMem_t tdSharedCachedMem1; } tiTdSharedMem_t; typedef struct _ag_resource_info { tiLoLevelResource_t tiLoLevelResource; /* Low level resource required */ tiInitiatorResource_t tiInitiatorResource; /* Initiator resource required */ tiTargetResource_t tiTargetResource; /* Target resource required */ tiTdSharedMem_t tiSharedMem; /* Shared memory by ti and td */ } ag_resource_info_t; /* ** Card info. for all cards and drivers */ #ifndef AGTIAPI_MEM_LIST_MAX #ifdef FC_TGT_BOARD_STRESS #define AGTIAPI_MEM_LIST_MAX 4096 /* max number of memory list */ #else #define AGTIAPI_MEM_LIST_MAX 1024 /* max number of memory list */ #endif #endif #ifndef AGTIAPI_DYNAMIC_MAX #define AGTIAPI_DYNAMIC_MAX 32 /* max unreleased dynamic memory */ #endif #define AGTIAPI_MAX_NAME 64 /* Max string name length */ typedef struct _ag_card_info { struct pci_dev *pPCIDev; /* PCI device pointer */ void *pCard; /* pointer to per card data structure */ U32 valid; /* valid structure */ S32 cardNameIndex; U32 cardID; /* card system ID */ U32 cardIdIndex; U32 pciIOAddrLow; /* PCI IOBASE lower */ U32 pciIOAddrUp; /* PCI IOBASE Upper */ U32_64 pciMemBase; /* PCI MEMBASE, physical */ caddr_t pciMemVirtAddr; /* PCI MEMBASE, virtual ptr */ U32 pciMemSize; /* PCI MEMBASE memory size */ struct task_struct *threadCtx; /* container for a worker thread */ #ifdef AGTIAPI_SA #ifdef FPGA_CARD U32_64 pciMemBase0; /* PCI MEMBASE, physical */ caddr_t pciMemVirtAddr0; /* PCI MEMBASE, virtual ptr */ U32 pciMemSize0; /* PCI MEMBASE memory size */ #endif #ifdef PMC_SPC U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; /* PCI MEMBASE, physical */ caddr_t pciMemVirtAddrSpc[PCI_NUMBER_BARS]; /* PCI MEMBASE, virtual ptr */ U32 pciMemSizeSpc[PCI_NUMBER_BARS]; /* PCI MEMBASE memory size */ #endif #endif #ifdef AGTIAPI_MSIX_INTR #define AGTIAPI_MSIX_NUM 9 /* Request 9 vectors */ char *irq_name[AGTIAPI_MSIX_NUM]; /* IRQ names */ struct msix_entry msix_table[AGTIAPI_MSIX_NUM]; /* Store msi vectors */ #endif U16 memBar; U16 memReg; U32 cacheIndex; U32 dmaIndex; ag_dma_addr_t tiDmaMem[AGTIAPI_MEM_LIST_MAX]; /* dma addr list */ ag_dma_addr_t dynamicMem[AGTIAPI_DYNAMIC_MAX]; /* dynamic mem list */ S08 *tiCachedMem[AGTIAPI_MEM_LIST_MAX]; /* cached mem list */ ag_resource_info_t tiRscInfo; /* low level resource requirement */ U08 WWN[AGTIAPI_MAX_NAME]; /* WWN for this card */ } ag_card_info_t; typedef enum { PORT_STATE_STOP, /* The port is stopped */ PORT_STATE_DOWN, /* we are initializing the port */ PORT_STATE_UP, /* port up and running */ PORT_STATE_READY, /* Port is ready to start Discovery */ PORT_STATE_RESETTING /* port is resetting */ } tdPortState_t; typedef struct tdhpRootOsData_s tdhpRootOsData_t; /* * TD Layer interrupt/non-interrupt context support structure for hpRoot_t. * The osData part of hpRoot is pointing to this tdhpRootOsData_t structure. */ struct tdhpRootOsData_s { tiRoot_t *tiRoot; /* Pointer back to tiRoot */ void *tdShared; /* Pointer to the shared TD area */ void *tdIni; /* Pointer to initiator specific TD area */ void *tdTgt; /* Pointer to target specific TD area */ agbool IntContext; /* Interrupt context */ bit32 queueId; /* Need HW support of queue pairs */ }; extern U32 ag_card_count; extern U32 ag_ini_card_count; extern ag_card_info_t agCardInfoList[32]; extern bit32 osChipRegWrite ( hpRoot_t *hpRoot, bit32 chipIOOffset, bit32 chipIOValue ); extern bit32 osChipRegRead ( hpRoot_t * hpRoot, bit32 chipIOOffset ); //extern pid_t g_sysStressd_pid; extern void qe8GetLocalStressNum(uint32_t *local_qe8_stress_num); extern int qe8GetPeerStressNum(void); #endif