/* QLogic (R)NIC Driver/Library * Copyright (c) 2015-2016 QLogic Corporation * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define __PREVENT_DUMP_MEM_ARR__ #define __PREVENT_PXP_GLOBAL_WIN__ #include "common_hsi.h" #include "qed.h" #include "qed_hsi.h" #include "qed_hw.h" #include "qed_reg_addr.h" #include "qed_sriov.h" #ifndef ASIC_ONLY #define QED_EMUL_FACTOR 2000 #define QED_FPGA_FACTOR 200 #endif #define QED_BAR_ACQUIRE_TIMEOUT 1000 /* Invalid values */ #define QED_BAR_INVALID_OFFSET (cpu_to_le32(-1)) struct qed_ptt { struct list_head list_entry; unsigned int idx; struct pxp_ptt_entry pxp; u8 hwfn_id; }; struct qed_ptt_pool { struct list_head free_list; spinlock_t lock; /* ptt synchronized access */ struct qed_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM]; }; void __qed_ptt_pool_free(struct qed_hwfn *p_hwfn) { kfree(p_hwfn->p_ptt_pool); p_hwfn->p_ptt_pool = NULL; } int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn) { struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL); int i; if (!p_pool) return -ENOMEM; INIT_LIST_HEAD(&p_pool->free_list); for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { p_pool->ptts[i].idx = i; p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET; p_pool->ptts[i].pxp.pretend.control = 0; p_pool->ptts[i].hwfn_id = p_hwfn->my_id; /* There are special PTT entries that are taken only by design. * The rest are added ot the list for general usage. */ if (i >= RESERVED_PTT_MAX) list_add(&p_pool->ptts[i].list_entry, &p_pool->free_list); } p_hwfn->p_ptt_pool = p_pool; spin_lock_init(&p_pool->lock); return 0; } void qed_ptt_invalidate(struct qed_hwfn *p_hwfn) { struct qed_ptt *p_ptt; int i; for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { p_ptt = &p_hwfn->p_ptt_pool->ptts[i]; p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET; } } void qed_ptt_pool_free(struct qed_hwfn *p_hwfn) { __qed_ptt_pool_free(p_hwfn); } struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn) { struct qed_ptt *p_ptt; unsigned int i; /* Take the free PTT from the list */ for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) { spin_lock_bh(&p_hwfn->p_ptt_pool->lock); if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) { p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list, struct qed_ptt, list_entry); list_del(&p_ptt->list_entry); spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "allocated ptt %d\n", p_ptt->idx); return p_ptt; } spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); usleep_range(1000, 2000); } DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n"); return NULL; } void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { /* This PTT should not be set to pretend if it is being released */ /* TODO - add some pretend sanity checks, to make sure pretend isn't set on this ptt */ spin_lock_bh(&p_hwfn->p_ptt_pool->lock); list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list); spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); } static u32 qed_ptt_get_hw_addr(struct qed_ptt *p_ptt) { /* The HW is using DWORDS and we need to translate it to Bytes */ return le32_to_cpu(p_ptt->pxp.offset) << 2; } static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt) { return PXP_PF_WINDOW_ADMIN_PER_PF_START + p_ptt->idx * sizeof(struct pxp_ptt_entry); } u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt) { return PXP_EXTERNAL_BAR_PF_WINDOW_START + p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE; } void qed_ptt_set_win(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 new_hw_addr) { u32 prev_hw_addr; prev_hw_addr = qed_ptt_get_hw_addr(p_ptt); if (new_hw_addr == prev_hw_addr) return; /* Update PTT entery in admin window */ DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Updating PTT entry %d to offset 0x%x\n", p_ptt->idx, new_hw_addr); /* The HW is using DWORDS and the address is in Bytes */ p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2); REG_WR(p_hwfn, qed_ptt_config_addr(p_ptt) + offsetof(struct pxp_ptt_entry, offset), le32_to_cpu(p_ptt->pxp.offset)); } static u32 qed_set_ptt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 hw_addr) { u32 win_hw_addr = qed_ptt_get_hw_addr(p_ptt); u32 offset; offset = hw_addr - win_hw_addr; if (p_ptt->hwfn_id != p_hwfn->my_id) DP_NOTICE(p_hwfn, "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n", p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id); /* Verify the address is within the window */ if (hw_addr < win_hw_addr || offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) { qed_ptt_set_win(p_hwfn, p_ptt, hw_addr); offset = 0; } return qed_ptt_get_bar_addr(p_ptt) + offset; } struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn, enum reserved_ptts ptt_idx) { if (ptt_idx >= RESERVED_PTT_MAX) { DP_NOTICE(p_hwfn, "Requested PTT %d is out of range\n", ptt_idx); return NULL; } return &p_hwfn->p_ptt_pool->ptts[ptt_idx]; } static bool qed_is_reg_fifo_empty(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { bool is_empty = true; u32 bar_addr; if (!p_hwfn->cdev->chk_reg_fifo) goto out; /* qed_rd() cannot be used here since it calls this function */ bar_addr = qed_set_ptt(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA); is_empty = REG_RD(p_hwfn, bar_addr) == 0; #ifndef ASIC_ONLY if (CHIP_REV_IS_SLOW(p_hwfn->cdev)) udelay(100); #endif out: return is_empty; } void qed_wr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 hw_addr, u32 val) { bool prev_fifo_err; u32 bar_addr; prev_fifo_err = !qed_is_reg_fifo_empty(p_hwfn, p_ptt); bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); REG_WR(p_hwfn, bar_addr, val); DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", bar_addr, hw_addr, val); #ifndef ASIC_ONLY if (CHIP_REV_IS_SLOW(p_hwfn->cdev)) udelay(100); #endif WARN(!prev_fifo_err && !qed_is_reg_fifo_empty(p_hwfn, p_ptt), "reg_fifo error was caused by a call to qed_wr(0x%x, 0x%x)\n", hw_addr, val); } u32 qed_rd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 hw_addr) { bool prev_fifo_err; u32 bar_addr, val; prev_fifo_err = !qed_is_reg_fifo_empty(p_hwfn, p_ptt); bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); val = REG_RD(p_hwfn, bar_addr); DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", bar_addr, hw_addr, val); #ifndef ASIC_ONLY if (CHIP_REV_IS_SLOW(p_hwfn->cdev)) udelay(100); #endif WARN(!prev_fifo_err && !qed_is_reg_fifo_empty(p_hwfn, p_ptt), "reg_fifo error was caused by a call to qed_rd(0x%x)\n", hw_addr); return val; } static void qed_memcpy_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, void *addr, u32 hw_addr, size_t n, bool to_device) { u32 dw_count, *host_addr, hw_offset; size_t quota, done = 0; u32 __iomem *reg_addr; while (done < n) { quota = min_t(size_t, n - done, PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE); if (IS_PF(p_hwfn->cdev)) { qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done); hw_offset = qed_ptt_get_bar_addr(p_ptt); } else { hw_offset = hw_addr + done; } dw_count = quota / 4; host_addr = (u32 *) ((u8 *) addr + done); reg_addr = (u32 __iomem *) REG_ADDR(p_hwfn, hw_offset); if (to_device) while (dw_count--) DIRECT_REG_WR(reg_addr++, *host_addr++); else while (dw_count--) *host_addr++ = DIRECT_REG_RD(reg_addr++); done += quota; } } void qed_memcpy_from(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n) { DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n", hw_addr, dest, hw_addr, (unsigned long)n); qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false); } void qed_memcpy_to(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n) { DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n", hw_addr, hw_addr, src, (unsigned long)n); qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true); } void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid) { u16 control = 0; SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); /* Every pretend undos previous pretends, including * previous port pretend. */ SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); p_ptt->pxp.pretend.control = cpu_to_le16(control); p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); REG_WR(p_hwfn, qed_ptt_config_addr(p_ptt) + offsetof(struct pxp_ptt_entry, pretend), *(u32 *) & p_ptt->pxp.pretend); } void qed_port_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 port_id) { u16 control = 0; SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); p_ptt->pxp.pretend.control = cpu_to_le16(control); REG_WR(p_hwfn, qed_ptt_config_addr(p_ptt) + offsetof(struct pxp_ptt_entry, pretend), *(u32 *) & p_ptt->pxp.pretend); } void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { u16 control = 0; SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); p_ptt->pxp.pretend.control = cpu_to_le16(control); REG_WR(p_hwfn, qed_ptt_config_addr(p_ptt) + offsetof(struct pxp_ptt_entry, pretend), *(u32 *) & p_ptt->pxp.pretend); } u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid) { u32 concrete_fid = 0; SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id); SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid); SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1); return concrete_fid; } #if 0 /* Ecore HW lock * ============= * Although the implemention is ready, today we don't have any flow that * utliizes said locks - and we want to keep it this way. * If this changes, this needs to be revisted. */ #define HW_LOCK_MAX_RETRIES 1000 int qed_hw_lock(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 resource, bool block) { u32 cnt, lock_status, hw_lock_cntr_reg; int qed_status; /* Locate the proper lock register for this function. * Note This code assumes all the H/W lock registers are sequential * in memory. */ hw_lock_cntr_reg = MISCS_REG_DRIVER_CONTROL_0 + p_hwfn->rel_pf_id * MISCS_REG_DRIVER_CONTROL_0_SIZE * sizeof(u32); /* Validate that the resource is not already taken */ lock_status = qed_rd(p_hwfn, p_ptt, hw_lock_cntr_reg); if (lock_status & resource) { DP_NOTICE(p_hwfn, "Resource already locked: lock_status=0x%x resource=0x%x\n", lock_status, resource); return -EBUSY; } /* Register for the lock */ qed_wr(p_hwfn, p_ptt, hw_lock_cntr_reg + sizeof(u32), resource); /* Try for 5 seconds every 5ms */ for (cnt = 0; cnt < HW_LOCK_MAX_RETRIES; cnt++) { lock_status = qed_rd(p_hwfn, p_ptt, hw_lock_cntr_reg); if (lock_status & resource) return 0; if (!block) { qed_status = -EBUSY; break; } usleep_range(5000, 10000); } if (cnt == HW_LOCK_MAX_RETRIES) { DP_NOTICE(p_hwfn, "Lock timeout resource=0x%x\n", resource); qed_status = -EBUSY; } /* Clear the pending request */ qed_wr(p_hwfn, p_ptt, hw_lock_cntr_reg, resource); return qed_status; } int qed_hw_unlock(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 resource) { u32 lock_status, hw_lock_cntr_reg; /* Locate the proper lock register for this function. * Note This code assumes all the H/W lock registers are sequential * in memory. */ hw_lock_cntr_reg = MISCS_REG_DRIVER_CONTROL_0 + p_hwfn->rel_pf_id * MISCS_REG_DRIVER_CONTROL_0_SIZE * sizeof(u32); /* Validate that the resource is currently taken */ lock_status = qed_rd(p_hwfn, p_ptt, hw_lock_cntr_reg); if (!(lock_status & resource)) { DP_NOTICE(p_hwfn, "resource 0x%x was not taken (lock status 0x%x)\n", resource, lock_status); return -ENODEV; } /* clear lock for resource */ qed_wr(p_hwfn, p_ptt, hw_lock_cntr_reg, resource); return 0; } #endif /* HW locks logic */ /* DMAE */ #define QED_DMAE_FLAGS_IS_SET(params, flag) \ ((params) != NULL && ((params)->flags & QED_DMAE_FLAG_ ## flag)) static void qed_dmae_opcode(struct qed_hwfn *p_hwfn, const u8 is_src_type_grc, const u8 is_dst_type_grc, struct qed_dmae_params *p_params) { u8 src_pfid, dst_pfid, port_id; u16 opcode_b = 0; u32 opcode = 0; /* Whether the source is the PCIe or the GRC. * 0- The source is the PCIe * 1- The source is the GRC. */ opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC : DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT; src_pfid = QED_DMAE_FLAGS_IS_SET(p_params, PF_SRC) ? p_params->src_pfid : p_hwfn->rel_pf_id; opcode |= (src_pfid & DMAE_CMD_SRC_PF_ID_MASK) << DMAE_CMD_SRC_PF_ID_SHIFT; /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC : DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT; dst_pfid = QED_DMAE_FLAGS_IS_SET(p_params, PF_DST) ? p_params->dst_pfid : p_hwfn->rel_pf_id; opcode |= (dst_pfid & DMAE_CMD_DST_PF_ID_MASK) << DMAE_CMD_DST_PF_ID_SHIFT; /* DMAE_E4_TODO need to check which value to specify here. */ /* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */ /* Whether to write a completion word to the completion destination: * 0-Do not write a completion word * 1-Write the completion word */ opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT; opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT; if (QED_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST)) opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT; /* swapping mode 3 - big endian there should be a define ifdefed in * the HSI somewhere. Since it is currently */ opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT; port_id = (QED_DMAE_FLAGS_IS_SET(p_params, PORT)) ? p_params->port_id : p_hwfn->port_id; opcode |= port_id << DMAE_CMD_PORT_ID_SHIFT; /* reset source address in next go */ opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT; /* reset dest address in next go */ opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT; /* SRC/DST VFID: all 1's - pf, otherwise VF id */ if (QED_DMAE_FLAGS_IS_SET(p_params, VF_SRC)) { opcode |= BIT(DMAE_CMD_SRC_VF_ID_VALID_SHIFT); opcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT); } else { opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK << DMAE_CMD_SRC_VF_ID_SHIFT); } if (QED_DMAE_FLAGS_IS_SET(p_params, VF_DST)) { opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT; opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT; } else { opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT; } p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode); p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b); } static u32 qed_dmae_idx_to_go_cmd(u8 idx) { BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4); /* All the DMAE 'go' registers form an array in internal memory */ return DMAE_REG_GO_C0 + (idx << 2); } static int qed_dmae_post_command(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd; u8 idx_cmd = p_hwfn->dmae_info.channel, i; int qed_status = 0; /* verify address is not NULL */ if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) || ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) { DP_NOTICE(p_hwfn, "source or destination address 0 idx_cmd=%d\n" "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", idx_cmd, le32_to_cpu(p_command->opcode), le16_to_cpu(p_command->opcode_b), le16_to_cpu(p_command->length_dw), le32_to_cpu(p_command->src_addr_hi), le32_to_cpu(p_command->src_addr_lo), le32_to_cpu(p_command->dst_addr_hi), le32_to_cpu(p_command->dst_addr_lo)); return -EINVAL; } DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", idx_cmd, le32_to_cpu(p_command->opcode), le16_to_cpu(p_command->opcode_b), le16_to_cpu(p_command->length_dw), le32_to_cpu(p_command->src_addr_hi), le32_to_cpu(p_command->src_addr_lo), le32_to_cpu(p_command->dst_addr_hi), le32_to_cpu(p_command->dst_addr_lo)); /* Copy the command to DMAE - need to do it before every call * for source/dest address no reset. * The number of commands have been increased to 16 (previous was 14) * The first 9 DWs are the command registers, the 10 DW is the * GO register, and * the rest are result registers (which are read only by the client). */ for (i = 0; i < DMAE_CMD_SIZE; i++) { u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ? *(((u32 *) p_command) + i) : 0; qed_wr(p_hwfn, p_ptt, DMAE_REG_CMD_MEM + (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) + (i * sizeof(u32)), data); } qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE); return qed_status; } int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn) { dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr; struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd; u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer; u32 **p_comp = &p_hwfn->dmae_info.p_completion_word; *p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(u32), p_addr, GFP_KERNEL); if (*p_comp == NULL) { DP_NOTICE(p_hwfn, "Failed to allocate `p_completion_word'\n"); goto err; } p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr; *p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(struct dmae_cmd), p_addr, GFP_KERNEL); if (*p_cmd == NULL) { DP_NOTICE(p_hwfn, "Failed to allocate `struct dmae_cmd'\n"); goto err; } p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr; *p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(u32) * DMAE_MAX_RW_SIZE, p_addr, GFP_KERNEL); if (*p_buff == NULL) { DP_NOTICE(p_hwfn, "Failed to allocate `intermediate_buffer'\n"); goto err; } p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id; p_hwfn->dmae_info.b_mem_ready = true; return 0; err: qed_dmae_info_free(p_hwfn); return -ENOMEM; } void qed_dmae_info_free(struct qed_hwfn *p_hwfn) { dma_addr_t p_phys; spin_lock_bh(&p_hwfn->dmae_info.lock); p_hwfn->dmae_info.b_mem_ready = false; spin_unlock_bh(&p_hwfn->dmae_info.lock); if (p_hwfn->dmae_info.p_completion_word != NULL) { p_phys = p_hwfn->dmae_info.completion_word_phys_addr; dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(u32), p_hwfn->dmae_info.p_completion_word, p_phys); p_hwfn->dmae_info.p_completion_word = NULL; } if (p_hwfn->dmae_info.p_dmae_cmd != NULL) { p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr; dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(struct dmae_cmd), p_hwfn->dmae_info.p_dmae_cmd, p_phys); p_hwfn->dmae_info.p_dmae_cmd = NULL; } if (p_hwfn->dmae_info.p_intermediate_buffer != NULL) { p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(u32) * DMAE_MAX_RW_SIZE, p_hwfn->dmae_info.p_intermediate_buffer, p_phys); p_hwfn->dmae_info.p_intermediate_buffer = NULL; } } static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn) { u32 wait_cnt_limit = 10000, wait_cnt = 0; int qed_status = 0; #ifndef ASIC_ONLY u32 factor = (CHIP_REV_IS_EMUL(p_hwfn->cdev) ? QED_EMUL_FACTOR : (CHIP_REV_IS_FPGA(p_hwfn->cdev) ? QED_FPGA_FACTOR : 1)); wait_cnt_limit *= factor; #endif /* DMAE_E4_TODO : TODO check if we have to call any other function * other than BARRIER to sync the completion_word since we are not * using the volatile keyword for this */ barrier(); while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) { udelay(DMAE_MIN_WAIT_TIME); if (++wait_cnt > wait_cnt_limit) { DP_NOTICE(p_hwfn->cdev, "Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n", *(p_hwfn->dmae_info.p_completion_word), DMAE_COMPLETION_VAL); qed_status = -EBUSY; break; } /* to sync the completion_word since we are not * using the volatile keyword for p_completion_word */ barrier(); } if (qed_status == 0) *p_hwfn->dmae_info.p_completion_word = 0; return qed_status; } static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u64 src_addr, u64 dst_addr, u8 src_type, u8 dst_type, u32 length_dw) { dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; int qed_status = 0; switch (src_type) { case QED_DMAE_ADDRESS_GRC: case QED_DMAE_ADDRESS_HOST_PHYS: cmd->src_addr_hi = cpu_to_le32(DMA_HI(src_addr)); cmd->src_addr_lo = cpu_to_le32(DMA_LO(src_addr)); break; /* for virtual source addresses we use the intermediate buffer. */ case QED_DMAE_ADDRESS_HOST_VIRT: cmd->src_addr_hi = cpu_to_le32(DMA_HI(phys)); cmd->src_addr_lo = cpu_to_le32(DMA_LO(phys)); memcpy(&(p_hwfn->dmae_info.p_intermediate_buffer[0]), (void *)(uintptr_t) src_addr, length_dw * sizeof(u32)); break; default: return -EINVAL; } switch (dst_type) { case QED_DMAE_ADDRESS_GRC: case QED_DMAE_ADDRESS_HOST_PHYS: cmd->dst_addr_hi = cpu_to_le32(DMA_HI(dst_addr)); cmd->dst_addr_lo = cpu_to_le32(DMA_LO(dst_addr)); break; /* for virtual destination addresses we use the intermediate buffer. */ case QED_DMAE_ADDRESS_HOST_VIRT: cmd->dst_addr_hi = cpu_to_le32(DMA_HI(phys)); cmd->dst_addr_lo = cpu_to_le32(DMA_LO(phys)); break; default: return -EINVAL; } cmd->length_dw = cpu_to_le16((u16) length_dw); qed_dmae_post_command(p_hwfn, p_ptt); qed_status = qed_dmae_operation_wait(p_hwfn); if (qed_status != 0) { DP_NOTICE(p_hwfn, "Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x, intermediate buffer 0x%llx.\n", src_addr, dst_addr, length_dw, (u64) p_hwfn->dmae_info. intermediate_buffer_phys_addr); return qed_status; } if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT) memcpy((void *)(uintptr_t) (dst_addr), &p_hwfn->dmae_info.p_intermediate_buffer[0], length_dw * sizeof(u32)); return 0; } static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u64 src_addr, u64 dst_addr, u8 src_type, u8 dst_type, u32 size_in_dwords, struct qed_dmae_params *p_params) { dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr; u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0; struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; u64 src_addr_split = 0, dst_addr_split = 0; u16 length_limit = DMAE_MAX_RW_SIZE; int qed_status = 0; u32 offset = 0; if (!p_hwfn->dmae_info.b_mem_ready) { DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "No buffers allocated. Avoid DMAE transaction [{src: addr 0x%llx, type %d}, {dst: addr 0x%llx, type %d}, size %d].\n", src_addr, src_type, dst_addr, dst_type, size_in_dwords); return -ENOMEM; } if (p_hwfn->cdev->recov_in_prog) { DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%llx, type %d}, {dst: addr 0x%llx, type %d}, size %d].\n", src_addr, src_type, dst_addr, dst_type, size_in_dwords); /* Return success to let the flow to be completed successfully * w/o any error handling. */ return 0; } if (!cmd) { DP_NOTICE(p_hwfn, "qed_dmae_execute_sub_operation failed. Invalid state. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n", src_addr, dst_addr, length_cur); return -EINVAL; } qed_dmae_opcode(p_hwfn, (src_type == QED_DMAE_ADDRESS_GRC), (dst_type == QED_DMAE_ADDRESS_GRC), p_params); cmd->comp_addr_lo = cpu_to_le32(DMA_LO(phys)); cmd->comp_addr_hi = cpu_to_le32(DMA_HI(phys)); cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL); /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */ cnt_split = size_in_dwords / length_limit; length_mod = size_in_dwords % length_limit; src_addr_split = src_addr; dst_addr_split = dst_addr; for (i = 0; i <= cnt_split; i++) { offset = length_limit * i; if (!QED_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) { if (src_type == QED_DMAE_ADDRESS_GRC) src_addr_split = src_addr + offset; else src_addr_split = src_addr + (offset * 4); } if (dst_type == QED_DMAE_ADDRESS_GRC) dst_addr_split = dst_addr + offset; else dst_addr_split = dst_addr + (offset * 4); length_cur = (cnt_split == i) ? length_mod : length_limit; /* might be zero on last iteration */ if (!length_cur) continue; qed_status = qed_dmae_execute_sub_operation(p_hwfn, p_ptt, src_addr_split, dst_addr_split, src_type, dst_type, length_cur); if (qed_status != 0) { DP_NOTICE(p_hwfn, "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n", qed_status, src_addr, dst_addr, length_cur); qed_hw_err_notify(p_hwfn, QED_HW_ERR_DMAE_FAIL); break; } } return qed_status; } int qed_dmae_host2grc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u64 source_addr, u32 grc_addr, u32 size_in_dwords, struct qed_dmae_params *p_params) { u32 grc_addr_in_dw = grc_addr / sizeof(u32); int rc; spin_lock_bh(&p_hwfn->dmae_info.lock); rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, grc_addr_in_dw, QED_DMAE_ADDRESS_HOST_VIRT, QED_DMAE_ADDRESS_GRC, size_in_dwords, p_params); spin_unlock_bh(&p_hwfn->dmae_info.lock); return rc; } int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 grc_addr, dma_addr_t dest_addr, u32 size_in_dwords, struct qed_dmae_params *p_params) { u32 grc_addr_in_dw = grc_addr / sizeof(u32); int rc; spin_lock_bh(&(p_hwfn->dmae_info.lock)); rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw, dest_addr, QED_DMAE_ADDRESS_GRC, QED_DMAE_ADDRESS_HOST_VIRT, size_in_dwords, p_params); spin_unlock_bh(&(p_hwfn->dmae_info.lock)); return rc; } int qed_dmae_host2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, dma_addr_t source_addr, dma_addr_t dest_addr, u32 size_in_dwords, struct qed_dmae_params *p_params) { int rc; spin_lock_bh(&p_hwfn->dmae_info.lock); rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, dest_addr, QED_DMAE_ADDRESS_HOST_PHYS, QED_DMAE_ADDRESS_HOST_PHYS, size_in_dwords, p_params); spin_unlock_bh(&p_hwfn->dmae_info.lock); return rc; } void qed_hw_err_notify(struct qed_hwfn *p_hwfn, enum qed_hw_err_type err_type) { /* Fan failure cannot be masked by handling of another HW error */ if (p_hwfn->cdev->recov_in_prog && err_type != QED_HW_ERR_FAN_FAIL) { DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "Recovery is in progress. Avoid notifying about HW error %d.\n", err_type); return; } qed_hw_error_occurred(p_hwfn, err_type); } int qed_dmae_sanity(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, const char *phase) { u32 size = PAGE_SIZE / 2, val; int rc = 0; dma_addr_t p_phys; void *p_virt; u32 *p_tmp; p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, &p_phys, GFP_KERNEL); if (!p_virt) { DP_NOTICE(p_hwfn, "DMAE sanity [%s]: failed to allocate memory\n", phase); return -ENOMEM; } /* Fill the bottom half of the allocated memory with a known pattern */ for (p_tmp = (u32 *) p_virt; p_tmp < (u32 *) ((u8 *) p_virt + size); p_tmp++) { /* Save the address itself as the value */ val = (u32) (uintptr_t) p_tmp; *p_tmp = val; } /* Zero the top half of the allocated memory */ memset((u8 *) p_virt + size, 0, size); DP_VERBOSE(p_hwfn, QED_MSG_SP, "DMAE sanity [%s]: src_addr={phys 0x%llx, virt %p}, dst_addr={phys 0x%llx, virt %p}, size 0x%x\n", phase, (u64) p_phys, p_virt, (u64) (p_phys + size), (u8 *) p_virt + size, size); rc = qed_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size, size / 4 /* size_in_dwords */ , NULL /* default parameters */ ); if (rc) { DP_NOTICE(p_hwfn, "DMAE sanity [%s]: qed_dmae_host2host() failed. rc = %d.\n", phase, rc); goto out; } /* Verify that the top half of the allocated memory has the pattern */ for (p_tmp = (u32 *) ((u8 *) p_virt + size); p_tmp < (u32 *) ((u8 *) p_virt + (2 * size)); p_tmp++) { /* The corresponding address in the bottom half */ val = (u32) (uintptr_t) p_tmp - size; if (*p_tmp != val) { DP_NOTICE(p_hwfn, "DMAE sanity [%s]: addr={phys 0x%llx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n", phase, (u64) p_phys + ((u8 *) p_tmp - (u8 *) p_virt), p_tmp, *p_tmp, val); rc = -EINVAL; goto out; } } out: dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, p_virt, p_phys); return rc; } void qed_ppfid_wr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 abs_ppfid, u32 hw_addr, u32 val) { u8 pfid = QED_PFID_BY_PPFID(p_hwfn, abs_ppfid); qed_fid_pretend(p_hwfn, p_ptt, pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); qed_wr(p_hwfn, p_ptt, hw_addr, val); qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); } u32 qed_ppfid_rd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 abs_ppfid, u32 hw_addr) { u8 pfid = QED_PFID_BY_PPFID(p_hwfn, abs_ppfid); u32 val; qed_fid_pretend(p_hwfn, p_ptt, pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); val = qed_rd(p_hwfn, p_ptt, hw_addr); qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); return val; }