/* QLogic (R)NIC Driver/Library * Copyright (c) 2015-2016 QLogic Corporation * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef _HAS_KTIME_GET_REAL_SECONDS /* QED_UPSTREAM */ #include #else #include #endif #include #include #define __PREVENT_DUMP_MEM_ARR__ #define __PREVENT_PXP_GLOBAL_WIN__ #define __PREVENT_COND_ARR__ #include "qed.h" #include "qed_sriov.h" #include "qed_sp.h" #include "qed_dev_api.h" #include "qed_ll2.h" #include "qed_fcoe.h" #include "qed_iscsi.h" #include "qed_mcp.h" #include "qed_reg_addr.h" #include "qed_compat.h" #include "qed_if.h" #include "qed_eth_if.h" #include "qed_ll2_if.h" #include "qed_selftest.h" #include "qed_hw.h" #include "qed_rdma.h" #include "qed_rdma_if.h" #include "qed_phy_api.h" static char version[] = "QLogic FastLinQ 4xxxx Core Module " DRV_MODULE_NAME " " DRV_MODULE_VERSION; MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_MODULE_VERSION); #ifndef QED_UPSTREAM static uint npar_tx_switching = 1; module_param(npar_tx_switching, uint, S_IRUGO); MODULE_PARM_DESC(npar_tx_switching, " Enable(1)/Disable(0) NPAR tx switching [Enabled by default]"); static uint qed_pkt_pacing; module_param(qed_pkt_pacing, uint, S_IRUGO); MODULE_PARM_DESC(qed_pkt_pacing, " Enable(1)/Disable(0) qed_pkt_pacing [Disabled by default]"); uint tx_switching = 1; module_param(tx_switching, uint, S_IRUGO); MODULE_PARM_DESC(tx_switching, " Enable(1)/Disable(0) per function tx switching [Enabled by default]"); static uint personality = QED_PCI_DEFAULT; module_param(personality, uint, S_IRUGO); MODULE_PARM_DESC(personality, " ETH=0, FCOE=1, ISCSI=2, ROCE=3, IWARP=4"); static uint pci_relax_order = QED_DEFAULT_RLX_ODR; module_param(pci_relax_order, uint, S_IRUGO); MODULE_PARM_DESC(pci_relax_order, " Do nothing=0, Enable=1, Disable=2 PCI relax ordering [Do nothing by default]"); enum { QED_MAX_DEVICES = 32, QED_DEVS_TBL_SIZE = QED_MAX_DEVICES + 1, QED_BDF2VAL_STR_SIZE = 512, QED_ENDOF_TBL = -1LL }; struct qed_bdf2val { u32 dbdf; int val; }; struct qed_bdf2val rdma_protocol_map_tbl[QED_DEVS_TBL_SIZE]; char rdma_protocol_map_str[QED_BDF2VAL_STR_SIZE]; module_param_string(rdma_protocol_map, rdma_protocol_map_str, sizeof(rdma_protocol_map_str), S_IRUGO); MODULE_PARM_DESC(rdma_protocol_map, "Determine the rdma protocol which will run on the device\n" "\t\tstring maps device function numbers to their requested protocol (e.g. '02:00.0-1,02:01.0-2').\n" "\t\tmaximum of 32 entries is supported\n" "\t\tValid values types: 0-Take default (what's configured on board, favors roce over iwarp) 1-none, 2-roce, 3-iwarp"); static uint drv_resc_alloc; module_param(drv_resc_alloc, uint, S_IRUGO); MODULE_PARM_DESC(drv_resc_alloc, " Force the driver's default resource allocation (0 do-not-force (default); 1 force)"); static uint chk_reg_fifo; module_param(chk_reg_fifo, uint, S_IRUGO); MODULE_PARM_DESC(chk_reg_fifo, " Check the reg_fifo after any register access (0 do-not-check (default); 1 check)"); static uint initiate_pf_flr = 1; module_param(initiate_pf_flr, uint, S_IRUGO); MODULE_PARM_DESC(initiate_pf_flr, " Initiate PF FLR as part of driver load (0 do-not-initiate; 1 initiate (default))"); static uint allow_mdump; module_param(allow_mdump, uint, S_IRUGO); MODULE_PARM_DESC(allow_mdump, " Allow the MFW to collect a crash dump (0 do-not-allow (default); 1 allow)"); static uint loopback_mode; module_param(loopback_mode, uint, S_IRUGO); MODULE_PARM_DESC(loopback_mode, " Force a loopback mode (0 no-loopback (default))"); static uint avoid_eng_reset; module_param(avoid_eng_reset, uint, S_IRUGO); MODULE_PARM_DESC(avoid_eng_reset, " Avoid engine reset when first PF loads on it (0 do-not-avoid (default); 1 avoid)"); static uint override_force_load; module_param(override_force_load, uint, S_IRUGO); MODULE_PARM_DESC(override_force_load, " Override the default force load behavior (0 do-not-override (default); 1 always; 2 never)"); static uint wc_disabled; module_param(wc_disabled, uint, S_IRUGO); MODULE_PARM_DESC(wc_disabled, " Write combine enabled/disabled (0 enabled (default); 1 disabled) (When disabling WC consider disabling EDPM too, via the module parameter roce_edpm, otherwise many EDPM failures can appear, resulting in even worse latency)"); static uint limit_msix_vectors; module_param(limit_msix_vectors, uint, S_IRUGO); MODULE_PARM_DESC(limit_msix_vectors, " Upper limit value for the requested number of MSI-X vectors. A value of 0 means no limit."); static uint limit_l2_queues; module_param(limit_l2_queues, uint, S_IRUGO); MODULE_PARM_DESC(limit_l2_queues, " Upper limit value for the number of L2 queues. A value of 0 means no limit."); static uint avoid_eng_affin; module_param(avoid_eng_affin, uint, S_IRUGO); MODULE_PARM_DESC(avoid_eng_affin, " Avoid engine affinity for RoCE/storage in case of CMT mode (0 do-not-avoid (default); 1 avoid)"); static uint ilt_page_size = 5; module_param(ilt_page_size, uint, S_IRUGO); MODULE_PARM_DESC(ilt_page_size, " Set the ILT page size (5 (default); allowed range for page sizes [3 - 12])"); static uint allow_vf_mac_change_mode = 0; module_param(allow_vf_mac_change_mode, uint, S_IRUGO); MODULE_PARM_DESC(allow_vf_mac_change_mode, " Allow VF to change MAC despite PF set force MAC (0 Disable (default); 1 Enable))"); #endif #if IS_ENABLED(CONFIG_QED_RDMA) /* ! QED_UPSTREAM */ /* RoCE configurations * ------------------- * The following must be supplied to QED during resource allocation as they * affect it, in specific, the ILT and the doorbell bar. Increasing the number * of QPs consumes ILT resources and increases the size of the normal region * in the doorbell bar.(TODO: update the following line if/when it becomes * obsolete) Increasing the number of DPIs increases the size of the PWM region * in the doorbell bar. * In practice the following algorithm is performed: * 1) Check if the number of QPs requested can reside in the ILT. If yes, * 2) Check if the number of QPs can reside in the normal region. If yes, * 3) Check if the remaining doorbell bar i.e. the PWM region, can contain * enough DPIs. Note that the size of a DPI varies according to the number * of CPUs. For more information Follow the algorithm itself * The actual numbers calculated according to the following use case: * - Bar size is 512kB * - Assume 8192 QPs => 16384 CIDs => Normal Region ~64kB (2048x4 byte DEMS) * the tilde is to account for L2, and core CIDs. * - This leaves ~448kB of BAR. * - Assume 32 CPU cores, since WID size is 1kB for we get 448/32 ~= 14 DPIs. * Hence we force at least 8. * (*) The full logic of this calculation is within QED. */ #define QED_RDMA_QPS (16384) #define QED_RDMA_DPIS (8) #define QED_ROCE_SRQS (8192) /* A single ILT page is used to allocate all of the XRC SRQs. For an ILT page * of 64kB this gives 910. */ #define QED_ROCE_XRC_SRQS (910) static uint num_rdma_qps = QED_RDMA_QPS; module_param(num_rdma_qps, uint, S_IRUGO); MODULE_PARM_DESC(num_rdma_qps, " The number of RDMA QPs is by default 16384 and can be raised ideally up to ~32k"); static uint num_roce_srqs = QED_ROCE_SRQS; module_param(num_roce_srqs, uint, S_IRUGO); MODULE_PARM_DESC(num_roce_srqs, " The number of RoCE SRQs is by default 8192 and can be raised ideally up to ~32k"); static uint num_roce_xrc_srqs = QED_ROCE_XRC_SRQS; static uint min_rdma_dpis = QED_RDMA_DPIS; module_param(min_rdma_dpis, uint, S_IRUGO); MODULE_PARM_DESC(min_rdma_dpis, " The minimum number of RDMA DPIs is by default 8 and can be lowered down to 4"); static uint roce_edpm; module_param(roce_edpm, uint, S_IRUGO); MODULE_PARM_DESC(roce_edpm, " The EDPM mode to load the driver with (0-Enable EDPM if BAR size is adequate, 1-Force EDPM (modprobe may fail on small BARs), 2-Disable EDPM)"); uint dcqcn_enable; module_param(dcqcn_enable, uint, S_IRUGO); MODULE_PARM_DESC(dcqcn_enable, " enable roce dcqcn."); #endif #define FW_FILE_VERSION \ __stringify(FW_MAJOR_VERSION) "." \ __stringify(FW_MINOR_VERSION) "." \ __stringify(FW_REVISION_VERSION) "." \ __stringify(FW_ENGINEERING_VERSION) #ifdef CONFIG_QED_ZIPPED_FW #define QED_FW_FILE_NAME \ "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin" #ifndef QED_UPSTREAM /* ! QED_UPSTREAM */ #define QED_FW_FILE_NAME_DUD \ "qed_init_values_zipped-" FW_FILE_VERSION ".bin" #endif #else #define QED_FW_FILE_NAME \ "qed/qed_init_values-" FW_FILE_VERSION ".bin" #endif MODULE_FIRMWARE(QED_FW_FILE_NAME); /* debugfs functions forward declarations */ void qed_dbg_init(void); void qed_dbg_exit(void); void qed_dbg_pf_init(struct qed_dev *cdev); void qed_dbg_pf_exit(struct qed_dev *cdev); #ifdef CONFIG_QED_RDMA /* ! QED_UPSTREAM */ static int qed_rdma_fill_protocol_map(void); #endif static int __init qed_init(void) { #ifdef CONFIG_QED_RDMA /* ! QED_UPSTREAM */ int rc; #endif pr_notice("qed_init called\n"); pr_info("%s\n", version); #ifdef CONFIG_QED_RDMA /* ! QED_UPSTREAM */ rc = qed_rdma_fill_protocol_map(); if (rc) return rc; #endif /* create debugfs node */ qed_dbg_init(); return 0; } static void __exit qed_cleanup(void) { pr_notice("qed_cleanup called\n"); /* destroy debugfs node */ qed_dbg_exit(); } module_init(qed_init); module_exit(qed_cleanup); /* Check if the DMA controller on the machine can properly handle the DMA * addressing required by the device. */ static int qed_set_coherency_mask(struct qed_dev *cdev) { struct device *dev = &cdev->pdev->dev; if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { DP_NOTICE(cdev, "Can't request 64-bit consistent allocations\n"); return -EIO; } } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n"); return -EIO; } return 0; } static void qed_free_pci(struct qed_dev *cdev) { struct pci_dev *pdev = cdev->pdev; if (cdev->doorbells && cdev->db_size) iounmap(cdev->doorbells); if (cdev->regview) iounmap(cdev->regview); if (atomic_read(&pdev->enable_cnt) == 1) pci_release_regions(pdev); pci_disable_device(pdev); } #define PCI_REVISION_ID_ERROR_VAL 0xff /* Performs PCI initializations as well as initializing PCI-related parameters * in the device structrue. Returns 0 in case of success. */ static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) { u8 rev_id; int rc; cdev->pdev = pdev; rc = pci_enable_device(pdev); if (rc) { DP_NOTICE(cdev, "Cannot enable PCI device\n"); goto err0; } if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { DP_NOTICE(cdev, "No memory region found in bar #0\n"); rc = -EIO; goto err1; } if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { DP_NOTICE(cdev, "No memory region found in bar #2\n"); rc = -EIO; goto err1; } if (atomic_read(&pdev->enable_cnt) == 1) { rc = pci_request_regions(pdev, DRV_MODULE_NAME); if (rc) { DP_NOTICE(cdev, "Failed to request PCI memory resources\n"); goto err1; } pci_set_master(pdev); pci_save_state(pdev); } pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); if (rev_id == PCI_REVISION_ID_ERROR_VAL) { DP_NOTICE(cdev, "Detected PCI device error [rev_id 0x%x]. Probably due to prior fan failure or over temperature indication. Aborting.\n", rev_id); rc = -ENODEV; goto err2; } if (!pci_is_pcie(pdev)) { DP_NOTICE(cdev, "The bus is not PCI Express\n"); rc = -EIO; goto err2; } cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); if (IS_PF(cdev) && cdev->pci_params.pm_cap == 0) { DP_NOTICE(cdev, "Cannot find power management capability\n"); /* FIXME - emulation currently has no PM (13_06_04) */ /* rc = -EIO; * goto err2; */ } rc = qed_set_coherency_mask(cdev); if (rc) goto err2; cdev->pci_params.mem_start = pci_resource_start(pdev, 0); cdev->pci_params.mem_end = pci_resource_end(pdev, 0); cdev->pci_params.irq = pdev->irq; cdev->regview = pci_ioremap_bar(pdev, 0); if (!cdev->regview) { DP_NOTICE(cdev, "Cannot map register space, aborting\n"); rc = -ENOMEM; goto err2; } cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2); cdev->db_size = pci_resource_len(cdev->pdev, 2); if (!cdev->db_size) { if (IS_PF(cdev)) { DP_NOTICE(cdev, "No Doorbell bar available\n"); return -EINVAL; } else { return 0; } } #ifndef QED_UPSTREAM if (wc_disabled) cdev->doorbells = ioremap_nocache(cdev->db_phys_addr, cdev->db_size); else cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); #else cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size); #endif if (!cdev->doorbells) { DP_NOTICE(cdev, "Cannot map doorbell space\n"); return -ENOMEM; } return 0; err2: pci_release_regions(pdev); err1: pci_disable_device(pdev); err0: return rc; } int qed_fill_dev_info(struct qed_dev *cdev, struct qed_dev_info *dev_info) { struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); struct qed_hw_info *hw_info = &p_hwfn->hw_info; struct qed_tunnel_info *tun = &cdev->tunnel; struct qed_ptt *ptt = NULL; memset(dev_info, 0, sizeof(struct qed_dev_info)); if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN && tun->vxlan.b_mode_enabled) dev_info->vxlan_enable = true; if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled && tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN && tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN) dev_info->gre_enable = true; if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled && tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN && tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN) dev_info->geneve_enable = true; dev_info->num_hwfns = cdev->num_hwfns; dev_info->pci_mem_start = cdev->pci_params.mem_start; dev_info->pci_mem_end = cdev->pci_params.mem_end; dev_info->pci_irq = cdev->pci_params.irq; dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn); dev_info->dev_type = cdev->type; ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr); if (IS_PF(cdev)) { dev_info->fw_major = FW_MAJOR_VERSION; dev_info->fw_minor = FW_MINOR_VERSION; dev_info->fw_rev = FW_REVISION_VERSION; dev_info->fw_eng = FW_ENGINEERING_VERSION; dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH, &cdev->mf_bits); if (!test_bit(QED_MF_DISABLE_ARFS, &cdev->mf_bits)) dev_info->b_arfs_capable = true; #ifndef QED_UPSTREAM dev_info->tx_switching = tx_switching ? true : false; #else dev_info->tx_switching = true; #endif if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_PME) dev_info->wol_support = true; dev_info->smart_an = qed_mcp_is_smart_an_supported(p_hwfn); ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); if (ptt) { qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt, &dev_info->mfw_rev, NULL); qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt, &dev_info->mbi_version); qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt, &dev_info->flash_size); qed_ptt_release(QED_LEADING_HWFN(cdev), ptt); } dev_info->abs_pf_id = p_hwfn->abs_pf_id; } else { qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major, &dev_info->fw_minor, &dev_info->fw_rev, &dev_info->fw_eng); qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL, &dev_info->mfw_rev, NULL); } dev_info->mtu = hw_info->mtu; return 0; } static void qed_free_cdev(struct qed_dev *cdev) { kfree((void *)cdev); } static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) { struct qed_dev *cdev; cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); if (!cdev) { pr_err("Failed to allocate cdev\n"); return cdev; } qed_init_struct(cdev); return cdev; } /* Sets the requested power state */ static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) { if (!cdev) return -ENODEV; /* FIXME - emulation currently does not support PM (13_06_04) */ DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n"); return 0; } static unsigned long qed_get_epoch_time(void) { #ifdef _HAS_KTIME_GET_REAL_SECONDS /* QED_UPSTREAM */ return ktime_get_real_seconds(); #else /* the get_seconds() interface is not y2038 safe on 32bit systems */ return get_seconds(); #endif } /* probing */ static struct qed_dev *qed_probe(struct pci_dev *pdev, struct qed_probe_params *params) { struct qed_hw_prepare_params hw_prepare_params; struct qed_dev *cdev; int rc; cdev = qed_alloc_cdev(pdev); if (!cdev) goto err0; cdev->drv_type = DRV_ID_DRV_TYPE_LINUX; cdev->protocol = params->protocol; if (params->is_vf) { cdev->b_is_vf = true; } qed_init_dp(cdev, params->dp_module, params->dp_level, NULL); cdev->recov_in_prog = params->recov_in_prog; rc = qed_init_pci(cdev, pdev); if (rc) { DP_ERR(cdev, "init pci failed\n"); goto err1; } DP_INFO(cdev, "PCI init completed successfully\n"); memset(&hw_prepare_params, 0, sizeof(hw_prepare_params)); #ifndef QED_UPSTREAM /* ! QED_UPSTREAM */ hw_prepare_params.personality = personality; hw_prepare_params.drv_resc_alloc = !!drv_resc_alloc; hw_prepare_params.chk_reg_fifo = !!chk_reg_fifo; hw_prepare_params.initiate_pf_flr = !!initiate_pf_flr; hw_prepare_params.allow_mdump = !!allow_mdump; hw_prepare_params.b_en_pacing = qed_pkt_pacing; #else hw_prepare_params.personality = QED_PCI_DEFAULT; hw_prepare_params.drv_resc_alloc = false; hw_prepare_params.chk_reg_fifo = false; hw_prepare_params.initiate_pf_flr = true; hw_prepare_params.allow_mdump = false; hw_prepare_params.b_en_pacing = false; #endif hw_prepare_params.epoch = (u32)qed_get_epoch_time(); rc = qed_hw_prepare(cdev, &hw_prepare_params); if (rc) { DP_ERR(cdev, "hw prepare failed\n"); goto err2; } #ifdef TEDIBEAR tedibear_create_bar(&cdev->hwfns[0]); #endif DP_INFO(cdev, "qed_probe completed successfully\n"); return cdev; err2: qed_free_pci(cdev); err1: qed_free_cdev(cdev); err0: return NULL; } static void qed_remove(struct qed_dev *cdev) { if (!cdev) return; qed_hw_remove(cdev); qed_free_pci(cdev); qed_set_power_state(cdev, PCI_D3hot); qed_free_cdev(cdev); } static void qed_disable_msix(struct qed_dev *cdev) { if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { pci_disable_msix(cdev->pdev); kfree(cdev->int_params.msix_table); } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) { pci_disable_msi(cdev->pdev); } memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param)); } static int qed_enable_msix(struct qed_dev *cdev, struct qed_int_params *int_params) { int i, rc, cnt; cnt = int_params->in.num_vectors; for (i = 0; i < cnt; i++) int_params->msix_table[i].entry = i; rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table, int_params->in.min_msix_cnt, cnt); if (rc < cnt && rc >= int_params->in.min_msix_cnt && (rc % cdev->num_hwfns)) { pci_disable_msix(cdev->pdev); /* If fastpath is initialized, we need at least one interrupt * per hwfn [and the slow path interrupts]. New requested number * should be a multiple of the number of hwfns. */ cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns; DP_NOTICE(cdev, "Trying to enable MSI-X with less vectors (%d out of %d)\n", cnt, int_params->in.num_vectors); rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table, cnt); if (!rc) rc = cnt; } if (rc > 0) { /* MSI-x configuration was achieved */ int_params->out.int_mode = QED_INT_MODE_MSIX; int_params->out.num_vectors = rc; rc = 0; } else { DP_NOTICE(cdev, "Failed to enable MSI-X [Requested %d vectors][rc %d]\n", cnt, rc); } return rc; } /* This function outputs the int mode and the number of enabled msix vector */ static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) { struct qed_int_params *int_params = &cdev->int_params; struct msix_entry *tbl; u8 info_str[20] = ""; int rc = 0, cnt; switch (int_params->in.int_mode) { case QED_INT_MODE_MSIX: /* Allocate MSIX table */ cnt = int_params->in.num_vectors; int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL); if (!int_params->msix_table) { rc = -ENOMEM; goto out; } /* Enable MSIX */ rc = qed_enable_msix(cdev, int_params); if (!rc) { snprintf(info_str, sizeof(info_str), " [%hd vectors]", int_params->out.num_vectors); goto out; } DP_NOTICE(cdev, "Failed to enable MSI-X\n"); kfree(int_params->msix_table); if (force_mode) goto out; /* Fallthrough */ case QED_INT_MODE_MSI: if (!QED_IS_CMT(cdev)) { rc = pci_enable_msi(cdev->pdev); if (!rc) { int_params->out.int_mode = QED_INT_MODE_MSI; goto out; } DP_NOTICE(cdev, "Failed to enable MSI\n"); if (force_mode) goto out; } /* Fallthrough */ case QED_INT_MODE_INTA: int_params->out.int_mode = QED_INT_MODE_INTA; rc = 0; goto out; default: DP_NOTICE(cdev, "Unknown int_mode value %d\n", int_params->in.int_mode); rc = -EINVAL; } out: if (!rc) DP_INFO(cdev, "Using %s interrupts%s\n", int_params->out.int_mode == QED_INT_MODE_INTA ? "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ? "MSI" : "MSIX", info_str); cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE; return rc; } static void qed_simd_handler_config(struct qed_dev *cdev, void *token, int index, void(*handler)(void *)) { struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; int relative_idx = index / cdev->num_hwfns; hwfn->simd_proto_handler[relative_idx].func = handler; hwfn->simd_proto_handler[relative_idx].token = token; } static void qed_simd_handler_clean(struct qed_dev *cdev, int index) { struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns]; int relative_idx = index / cdev->num_hwfns; memset(&hwfn->simd_proto_handler[relative_idx], 0, sizeof(struct qed_simd_fp_handler)); } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) /* QED_UPSTREAM */ static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) #else static irqreturn_t qed_msix_sp_int(int irq, void *tasklet, struct pt_regs *regs) #endif { tasklet_schedule((struct tasklet_struct *)tasklet); return IRQ_HANDLED; } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) /* QED_UPSTREAM */ static irqreturn_t qed_single_int(int irq, void *dev_instance) #else static irqreturn_t qed_single_int(int irq, void *dev_instance, struct pt_regs *regs) #endif { struct qed_dev *cdev = (struct qed_dev *)dev_instance; struct qed_hwfn *hwfn; irqreturn_t rc = IRQ_NONE; u64 status; int i, j; for (i = 0; i < cdev->num_hwfns; i++) { status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]); if (!status) continue; hwfn = &cdev->hwfns[i]; /* Slowpath interrupt */ if (unlikely(status & 0x1)) { tasklet_schedule(hwfn->sp_dpc); status &= ~0x1; rc = IRQ_HANDLED; } /* Fastpath interrupts */ for (j = 0; j < 64; j++) { if ((0x2ULL << j) & status) { struct qed_simd_fp_handler *p_handler = &hwfn->simd_proto_handler[j]; if (p_handler) p_handler->func(p_handler->token); else DP_NOTICE(hwfn, "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n", j, status); status &= ~(0x2ULL << j); rc = IRQ_HANDLED; } } if (unlikely(status)) DP_VERBOSE(hwfn, NETIF_MSG_INTR, "got an unknown interrupt status 0x%llx\n", status); } return rc; } int qed_slowpath_irq_req(struct qed_hwfn *hwfn) { struct qed_dev *cdev = hwfn->cdev; u32 int_mode; int rc = 0; u8 id; int_mode = cdev->int_params.out.int_mode; if (int_mode == QED_INT_MODE_MSIX) { id = hwfn->my_id; snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x", id, cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); rc = request_irq(cdev->int_params.msix_table[id].vector, qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc); } else { unsigned long flags = 0; snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x", cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), PCI_FUNC(cdev->pdev->devfn)); if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA) flags |= IRQF_SHARED; rc = request_irq(cdev->pdev->irq, qed_single_int, flags, cdev->name, cdev); } if (rc) DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc); else DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP), "Requested slowpath %s\n", (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ"); return rc; } static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn) { /* Calling the disable function will make sure that any * currently-running function is completed. The following call to the * enable function makes this sequence a flush-like operation. */ if (p_hwfn->b_sp_dpc_enabled) { tasklet_disable(p_hwfn->sp_dpc); tasklet_enable(p_hwfn->sp_dpc); } } void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn) { struct qed_dev *cdev = p_hwfn->cdev; u8 id = p_hwfn->my_id; u32 int_mode; int_mode = cdev->int_params.out.int_mode; if (int_mode == QED_INT_MODE_MSIX) synchronize_irq(cdev->int_params.msix_table[id].vector); else synchronize_irq(cdev->pdev->irq); qed_slowpath_tasklet_flush(p_hwfn); } static void qed_slowpath_irq_free(struct qed_dev *cdev) { int i; if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { for_each_hwfn(cdev, i) { if (!cdev->hwfns[i].b_int_requested) break; synchronize_irq(cdev->int_params.msix_table[i].vector); free_irq(cdev->int_params.msix_table[i].vector, cdev->hwfns[i].sp_dpc); } } else { /* @@@TODO - correct squence for freeing INTA ? */ if (QED_LEADING_HWFN(cdev)->b_int_requested) free_irq(cdev->pdev->irq, cdev); } qed_int_disable_post_isr_release(cdev); } static int qed_nic_stop(struct qed_dev *cdev) { int i, rc; rc = qed_hw_stop(cdev); for (i = 0; i < cdev->num_hwfns; i++) { struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; if (p_hwfn->b_sp_dpc_enabled) { tasklet_disable(p_hwfn->sp_dpc); p_hwfn->b_sp_dpc_enabled = false; DP_VERBOSE(cdev, NETIF_MSG_IFDOWN, "Disabled sp taskelt [hwfn %d] at %p\n", i, p_hwfn->sp_dpc); } } qed_dbg_pf_exit(cdev); return rc; } static int qed_nic_setup(struct qed_dev *cdev) { int rc, i; /* Determine if interface is going to require LL2 */ if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) { for (i = 0; i < cdev->num_hwfns; i++) { struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; p_hwfn->using_ll2 = true; } } #ifndef QED_UPSTREAM qed_set_ilt_page_size(cdev, (u8)ilt_page_size); #else qed_set_ilt_page_size(cdev, 5); #endif rc = qed_resc_alloc(cdev); if (rc) return rc; DP_INFO(cdev, "Allocated qed resources\n"); qed_resc_setup(cdev); return rc; } static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) { int limit = 0; /* Mark the fastpath as free/used */ cdev->int_params.fp_initialized = cnt ? true : false; if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) limit = cdev->num_hwfns * 63; else if (cdev->int_params.fp_msix_cnt) limit = cdev->int_params.fp_msix_cnt; if (!limit) return -ENOMEM; return min_t(int, cnt, limit); } static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) { memset(info, 0, sizeof(struct qed_int_info)); if (!cdev->int_params.fp_initialized) { DP_INFO(cdev, "Protocol driver requested interrupt information, but its support is not yet configured\n"); return -EINVAL; } /* Need to expose only MSI-X information; Single IRQ is handled solely * by qed. */ if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { int msix_base = cdev->int_params.fp_msix_base; info->msix_cnt = cdev->int_params.fp_msix_cnt; info->msix = &cdev->int_params.msix_table[msix_base]; } return 0; } static void qed_slowpath_setup_msix(struct qed_dev *cdev) { int i; /* Divide allocated MSI-X vectors between slowpath and fastpath */ cdev->int_params.fp_msix_base = cdev->num_hwfns; cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors - cdev->num_hwfns; DP_VERBOSE(cdev, NETIF_MSG_INTR, "fp_msix_base %d, fp_msix_cnt %d\n", cdev->int_params.fp_msix_base, cdev->int_params.fp_msix_cnt); /* The actual number of L2 queues depends on the number of: * (1) requested connections, (2) allocated L2 queues, and (3) available * MSI-X vectors. */ if (QED_IS_L2_PERSONALITY(QED_LEADING_HWFN(cdev))) { struct qed_hwfn *p_hwfn; for_each_hwfn(cdev, i) { u16 l2_queues, cids; p_hwfn = &cdev->hwfns[i]; l2_queues = (u16)FEAT_NUM(p_hwfn, QED_PF_L2_QUE); cids = p_hwfn->pf_params.eth_pf_params.num_cons; cids /= 2 /* rx and xdp */ + p_hwfn->hw_info.num_hw_tc; cdev->num_l2_queues += min_t(u16, l2_queues, cids); } cdev->num_l2_queues = min_t(u16, cdev->num_l2_queues, cdev->int_params.fp_msix_cnt); p_hwfn = QED_LEADING_HWFN(cdev); DP_VERBOSE(cdev, NETIF_MSG_INTR, "num_l2_queues %d [num_hwfns %d, FEAT_NUM[PF_L2_QUEUE] %d, num_cons %d, fp_msix_cnt %d]\n", cdev->num_l2_queues, cdev->num_hwfns, FEAT_NUM(p_hwfn, QED_PF_L2_QUE), p_hwfn->pf_params.eth_pf_params.num_cons, cdev->int_params.fp_msix_cnt); #ifndef QED_UPSTREAM if (limit_l2_queues && cdev->num_l2_queues > limit_l2_queues) { DP_INFO(cdev, "Limit the number of L2 queues to %hd [original value = %hd]\n", limit_l2_queues, cdev->num_l2_queues); cdev->num_l2_queues = limit_l2_queues; } #endif } /* Need to further split the fastpath interrupts between L2 and RDMA */ if (IS_ENABLED(CONFIG_QED_RDMA) && QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) { if (cdev->int_params.fp_msix_cnt > cdev->num_l2_queues) { cdev->int_params.rdma_msix_base = cdev->int_params.fp_msix_base + cdev->num_l2_queues; cdev->int_params.rdma_msix_cnt = (cdev->int_params.fp_msix_cnt - cdev->num_l2_queues) / cdev->num_hwfns; /* RDMA uses a single engine */ cdev->int_params.fp_msix_cnt = cdev->num_l2_queues; } else { /* Disable RDMA since no MSI-X vectors are available */ cdev->int_params.rdma_msix_cnt = 0; } DP_VERBOSE(cdev, (NETIF_MSG_INTR | QED_MSG_RDMA), "rdma_msix_base %d, rdma_msix_cnt %d\n", cdev->int_params.rdma_msix_base, cdev->int_params.rdma_msix_cnt); } } static int qed_slowpath_setup_int(struct qed_dev *cdev, enum qed_int_mode int_mode) { struct qed_sb_cnt_info sb_cnt_info; int i, rc; if ((int_mode == QED_INT_MODE_MSI) && QED_IS_CMT(cdev)) { DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); return -EINVAL; } memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); cdev->int_params.in.int_mode = int_mode; /* @@@TBD - request MSIX entries which suffice for all vectors assigned * to that Interface in the IGU CAM. There should probably be some * additional limits to this value. */ for_each_hwfn(cdev, i) { memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info); cdev->int_params.in.num_vectors += sb_cnt_info.cnt; cdev->int_params.in.num_vectors++; /* slowpath */ } /* We want a minimum of one slowpath and one fastpath vector per hwfn */ cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2; if (is_kdump_kernel()) { DP_INFO(cdev, "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n", cdev->int_params.in.min_msix_cnt); cdev->int_params.in.num_vectors = cdev->int_params.in.min_msix_cnt; } #ifndef QED_UPSTREAM if (limit_msix_vectors && cdev->int_params.in.num_vectors > limit_msix_vectors) { DP_INFO(cdev, "Limit the max number of requested MSI-X vectors to %hd [original value = %hd]\n", limit_msix_vectors, cdev->int_params.in.num_vectors); cdev->int_params.in.num_vectors = limit_msix_vectors; } #endif rc = qed_set_int_mode(cdev, false); if (rc) { DP_ERR(cdev, "qed_slowpath_setup_int ERR\n"); return rc; } if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) qed_slowpath_setup_msix(cdev); return 0; } static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) { u8 vectors = 0; int rc; memset(&cdev->int_params, 0, sizeof(struct qed_int_params)); cdev->int_params.in.int_mode = QED_INT_MODE_MSIX; qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &vectors); cdev->int_params.in.num_vectors = vectors; if (QED_IS_CMT(cdev)) { qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors); cdev->int_params.in.num_vectors += vectors; } /* We want a minimum of one fastpath vector per vf hwfn */ cdev->int_params.in.min_msix_cnt = cdev->num_hwfns; rc = qed_set_int_mode(cdev, true); if (rc) return rc; cdev->int_params.fp_msix_base = 0; cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors; return 0; } u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, u8 *input_buf, u32 max_size, u8 *unzip_buf) { int rc; p_hwfn->stream->next_in = input_buf; p_hwfn->stream->avail_in = input_len; p_hwfn->stream->next_out = unzip_buf; p_hwfn->stream->avail_out = max_size; rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS); if (rc != Z_OK) { DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n", rc); return 0; } rc = zlib_inflate(p_hwfn->stream, Z_FINISH); zlib_inflateEnd(p_hwfn->stream); if (rc != Z_OK && rc != Z_STREAM_END) { DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n", p_hwfn->stream->msg, rc); return 0; } return p_hwfn->stream->total_out / 4; } static int qed_alloc_stream_mem(struct qed_dev *cdev) { int i; void *workspace; for_each_hwfn(cdev, i) { struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL); if (!p_hwfn->stream) return -ENOMEM; workspace = vzalloc(zlib_inflate_workspacesize()); if (!workspace) return -ENOMEM; p_hwfn->stream->workspace = workspace; } return 0; } static void qed_free_stream_mem(struct qed_dev *cdev) { int i; for_each_hwfn(cdev, i) { struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; if (!p_hwfn->stream) return; vfree(p_hwfn->stream->workspace); kfree(p_hwfn->stream); } } #ifdef CONFIG_QED_RDMA /* ! QED_UPSTREAM */ #define QED_BDF_TO_VAL_SIZE 9 /* xx:xx.x-p */ /* function up to 4 bits, device takes up to 8 bits */ #define QED_BDF_TO_DBDF(_bus, _dev, _fn) \ (((_bus) << 12) | ((_dev) << 4) | (_fn)) static int qed_rdma_get_protocol(struct pci_dev *pdev) { int i = 1; u32 dbdf; int val; val = rdma_protocol_map_tbl[0].val; if (!pdev) return val; if (!pdev->bus) { pr_debug("qed: pci_dev without valid bus number\n"); return val; } dbdf = QED_BDF_TO_DBDF(pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); while ((i < QED_DEVS_TBL_SIZE) && (rdma_protocol_map_tbl[i].dbdf != QED_ENDOF_TBL)) { if (rdma_protocol_map_tbl[i].dbdf == dbdf) { val = rdma_protocol_map_tbl[i].val; return val; } i++; } return val; } static int qed_rdma_fill_protocol_map(void) { int bus, dev, fn, protocol; int j, i = 1; u32 dbdf; char *p; p = rdma_protocol_map_str; /* First entry will always be default incase no match is found */ rdma_protocol_map_tbl[0].val = QED_RDMA_PROTOCOL_DEFAULT; rdma_protocol_map_tbl[1].dbdf = QED_ENDOF_TBL; if (strlen(p) == 0) return 0; while (strlen(p) >= QED_BDF_TO_VAL_SIZE) { if (i >= QED_DEVS_TBL_SIZE) { pr_warn("qed module parameter rdma_protocol_map: Too many devices\n"); goto err; } if (sscanf(p, "%02x:%02x.%x-%d", &bus, &dev, &fn, &protocol) != 4) { /* expected 4 values matching the scan format */ pr_err("qed module parameter rdma_protocol_map: Invalid bdf:%s\n", p); goto err; } dbdf = QED_BDF_TO_DBDF(bus, dev, fn); for (j = 1; j < i; j++) if (rdma_protocol_map_tbl[j].dbdf == dbdf) { pr_warn("qed module parameter rdma_protocol_map: %02x:%02x.%x appears multiple times\n", bus, dev, fn); goto err; } if (protocol > QED_RDMA_PROTOCOL_IWARP) { pr_warn("qed module parameter rdma_protocol_map: Protocol value out of range %d\n", protocol); goto err; } rdma_protocol_map_tbl[i].val = protocol; rdma_protocol_map_tbl[i].dbdf = dbdf; p += QED_BDF_TO_VAL_SIZE; if (strlen(p)) { if (*p == ',') { p++; /* separator */ } else { pr_warn("qed module parameter rdma_protocol_map: Separator invalid %c, expecting ,\n", *p); goto err; } } i++; if (i < QED_DEVS_TBL_SIZE) rdma_protocol_map_tbl[i].dbdf = QED_ENDOF_TBL; } if (strlen(p)) { pr_warn("qed module parameter rdma_protocol_map: Invalid value %s\n", p); goto err; } return 0; err: rdma_protocol_map_tbl[1].dbdf = QED_ENDOF_TBL; pr_warn("qed: The value of rdma_protocol_map is incorrect!\n"); return -EINVAL; } #endif static void qed_update_pf_params(struct qed_dev *cdev, struct qed_pf_params *params) { int i; if (IS_ENABLED(CONFIG_QED_RDMA)) { #ifndef TEDIBEAR /* ! QED_UPSTREAM */ /* Sadly, the dynamic isn't sufficient alone since the module * parameters would be compiled-out. So we need to wrap them * as well. */ params->rdma_pf_params.num_qps = num_rdma_qps; params->rdma_pf_params.num_srqs = num_roce_srqs; params->rdma_pf_params.num_xrc_srqs = num_roce_xrc_srqs; params->rdma_pf_params.min_dpis = min_rdma_dpis; /* divide by 3 the MRs to avoid MF ILT overflow */ params->rdma_pf_params.roce_edpm_mode = roce_edpm; params->rdma_pf_params.enable_dcqcn = dcqcn_enable; params->rdma_pf_params.rdma_protocol = qed_rdma_get_protocol(cdev->pdev); #endif params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; } if (QED_IS_CMT(cdev) || IS_VF(cdev)) params->eth_pf_params.num_arfs_filters = 0; /* In case we might support RDMA, don't allow qede to be greedy * with the L2 contexts. Allow for 64 queues [rx, tx coses, xdp] * per hwfn. */ if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) { u16 *num_cons; num_cons = ¶ms->eth_pf_params.num_cons; *num_cons = min_t(u16, *num_cons, 384/* 64 * 6 */); } #ifndef QED_UPSTREAM params->eth_pf_params.allow_vf_mac_change = allow_vf_mac_change_mode; #endif for (i = 0; i < cdev->num_hwfns; i++) { struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; p_hwfn->pf_params = *params; } } static void qed_slowpath_wq_stop(struct qed_dev *cdev) { int i; if (IS_VF(cdev)) return; for_each_hwfn(cdev, i) { if (!cdev->hwfns[i].slowpath_wq) continue; flush_workqueue(cdev->hwfns[i].slowpath_wq); destroy_workqueue(cdev->hwfns[i].slowpath_wq); } } void qed_slowpath_task(struct work_struct *work) { struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn, slowpath_task.work); struct qed_ptt *ptt = qed_ptt_acquire(hwfn); if (!ptt) { queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); return; } if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags)) qed_mfw_process_tlv_req(hwfn, ptt); qed_ptt_release(hwfn, ptt); } int qed_slowpath_wq_start(struct qed_dev *cdev) { struct qed_hwfn *hwfn; char name[NAME_SIZE]; int i; if (IS_VF(cdev)) return 0; for_each_hwfn(cdev, i) { hwfn = &cdev->hwfns[i]; snprintf(name, NAME_SIZE, "slowpath-%02x:%02x.%02x", cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id); #ifdef _HAS_ALLOC_WORKQUEUE /* QED_UPSTREAM */ hwfn->slowpath_wq = alloc_workqueue(name, 0, 0); #else hwfn->slowpath_wq = create_singlethread_workqueue(name); #endif if (!hwfn->slowpath_wq) { DP_NOTICE(hwfn, "Cannot create slowpath workqueue\n"); return -ENOMEM; } INIT_DELAYED_WORK(&hwfn->slowpath_task, qed_slowpath_task); } return 0; } static int qed_slowpath_start(struct qed_dev *cdev, struct qed_slowpath_params *params) { struct qed_drv_load_params drv_load_params; struct qed_hw_init_params hw_init_params; struct qed_mcp_drv_version drv_version; #ifdef QED_ENC_SUPPORTED struct qed_tunnel_info tunn_info; #endif bool allow_npar_tx_switching; const u8 *data = NULL; struct qed_hwfn *hwfn; struct qed_ptt *p_ptt; int rc = -ENOMEM; if (qed_iov_wq_start(cdev)) goto err; if (qed_slowpath_wq_start(cdev)) goto err; if (IS_PF(cdev)) { #ifdef CONFIG_QED_BINARY_FW rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME, &cdev->pdev->dev); if (rc) { #ifndef QED_UPSTREAM /* ! QED_UPSTREAM */ /* There are isses in some DUD-based installations; See * CQ85839 for reference. */ rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME_DUD, &cdev->pdev->dev); if (rc) { DP_NOTICE(cdev, "Failed to find fw file - /lib/firmware/%s and /lib/firmware/%s\n", QED_FW_FILE_NAME_DUD, QED_FW_FILE_NAME); goto err; } #else DP_NOTICE(cdev, "Failed to find fw file - /lib/firmware/%s\n", QED_FW_FILE_NAME); goto err; #endif } #endif if (!QED_IS_CMT(cdev)) { p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev)); if (p_ptt) { QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt; } else { DP_NOTICE(cdev, "Failed to acquire PTT for aRFS\n"); goto err; } } } cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS; rc = qed_nic_setup(cdev); if (rc) goto err; if (IS_PF(cdev)) rc = qed_slowpath_setup_int(cdev, params->int_mode); else rc = qed_slowpath_vf_setup_int(cdev); if (rc) goto err1; if (IS_PF(cdev)) { /* Allocate stream for unzipping */ rc = qed_alloc_stream_mem(cdev); if (rc) { DP_NOTICE(cdev, "Failed to allocate stream memory\n"); goto err2; } } #ifdef CONFIG_QED_BINARY_FW /* First Dword used to diffrentiate between various sources */ if (IS_PF(cdev)) data = cdev->firmware->data + sizeof(u32); #endif #ifndef QED_UPSTREAM allow_npar_tx_switching = npar_tx_switching ? true : false; #else allow_npar_tx_switching = true; #endif if (IS_PF(cdev)) qed_dbg_pf_init(cdev); /* Start the slowpath */ memset(&hw_init_params, 0, sizeof(hw_init_params)); #ifdef QED_ENC_SUPPORTED memset(&tunn_info, 0, sizeof(tunn_info)); tunn_info.vxlan.b_mode_enabled = true; tunn_info.l2_gre.b_mode_enabled = true; tunn_info.ip_gre.b_mode_enabled = true; tunn_info.l2_geneve.b_mode_enabled = true; tunn_info.ip_geneve.b_mode_enabled = true; tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN; tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN; tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN; hw_init_params.p_tunn = &tunn_info; #endif hw_init_params.b_hw_start = true; hw_init_params.int_mode = cdev->int_params.out.int_mode; hw_init_params.allow_npar_tx_switch = allow_npar_tx_switching; hw_init_params.bin_fw_data = data; #ifndef QED_UPSTREAM hw_init_params.pci_rlx_odr_mode = pci_relax_order; #endif memset(&drv_load_params, 0, sizeof(drv_load_params)); drv_load_params.is_crash_kernel = is_kdump_kernel(); /* TODO - add "&& !kdump_over_pda" */ drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT; #ifndef QED_UPSTREAM drv_load_params.avoid_eng_reset = !!avoid_eng_reset; drv_load_params.override_force_load = (override_force_load == 1) ? QED_OVERRIDE_FORCE_LOAD_ALWAYS : (override_force_load == 2) ? QED_OVERRIDE_FORCE_LOAD_NEVER : QED_OVERRIDE_FORCE_LOAD_NONE; hw_init_params.avoid_eng_affin = !!avoid_eng_affin; #else drv_load_params.avoid_eng_reset = false; drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE; hw_init_params.avoid_eng_affin = false; #endif hw_init_params.p_drv_load_params = &drv_load_params; rc = qed_hw_init(cdev, &hw_init_params); if (rc) goto err2; DP_INFO(cdev, "HW initialization and function start completed successfully\n"); if (IS_PF(cdev)) { cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) | BIT(QED_MODE_L2GENEVE_TUNN) | BIT(QED_MODE_IPGENEVE_TUNN) | BIT(QED_MODE_L2GRE_TUNN) | BIT(QED_MODE_IPGRE_TUNN)); } /* Allocate LL2 interface if needed */ if (QED_LEADING_HWFN(cdev)->using_ll2) { rc = qed_ll2_alloc_if(cdev); if (rc) goto err3; } if (IS_PF(cdev)) { hwfn = QED_LEADING_HWFN(cdev); drv_version.version = (params->drv_major << 24) | (params->drv_minor << 16) | (params->drv_rev << 8) | (params->drv_eng); strlcpy(drv_version.name, params->name, MCP_DRV_VER_STR_SIZE - 4); rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, &drv_version); if (rc) { DP_NOTICE(cdev, "Failed sending drv version command\n"); return rc; } } qed_reset_vport_stats(cdev); return 0; err3: qed_hw_stop(cdev); err2: qed_hw_timers_stop_all(cdev); /* TODO - need to handle possible failure during init */ if (IS_PF(cdev)) qed_slowpath_irq_free(cdev); qed_copy_bus_to_postconfig(cdev, qed_get_debug_engine(cdev)); qed_free_stream_mem(cdev); qed_disable_msix(cdev); err1: qed_resc_free(cdev); err: #ifdef CONFIG_QED_BINARY_FW if (IS_PF(cdev)) release_firmware(cdev->firmware); #endif if (IS_PF(cdev) && !QED_IS_CMT(cdev) && QED_LEADING_HWFN(cdev)->p_arfs_ptt) qed_ptt_release(QED_LEADING_HWFN(cdev), QED_LEADING_HWFN(cdev)->p_arfs_ptt); qed_iov_wq_stop(cdev, false); qed_slowpath_wq_stop(cdev); return rc; } static int qed_slowpath_stop(struct qed_dev *cdev) { if (!cdev) return -ENODEV; qed_slowpath_wq_stop(cdev); qed_ll2_dealloc_if(cdev); if (IS_PF(cdev)) { if (!QED_IS_CMT(cdev)) qed_ptt_release(QED_LEADING_HWFN(cdev), QED_LEADING_HWFN(cdev)->p_arfs_ptt); qed_free_stream_mem(cdev); if (IS_QED_ETH_IF(cdev)) qed_sriov_disable(cdev, true); } qed_nic_stop(cdev); if (IS_PF(cdev)) qed_slowpath_irq_free(cdev); qed_disable_msix(cdev); qed_resc_free(cdev); qed_iov_wq_stop(cdev, true); #ifdef CONFIG_QED_BINARY_FW if (IS_PF(cdev)) release_firmware(cdev->firmware); #endif return 0; } static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE]) { int i; memcpy(cdev->name, name, NAME_SIZE); for_each_hwfn(cdev, i) snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); } static u32 qed_sb_init(struct qed_dev *cdev, struct qed_sb_info *sb_info, void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id, enum qed_sb_type type) { struct qed_hwfn *p_hwfn; struct qed_ptt *p_ptt; u16 rel_sb_id; u32 rc; /* RoCE/Storage use a single engine in CMT mode while L2 uses both */ if (type == QED_SB_TYPE_L2_QUEUE) { p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns]; rel_sb_id = sb_id / cdev->num_hwfns; } else { p_hwfn = QED_AFFIN_HWFN(cdev); rel_sb_id = sb_id; } DP_VERBOSE(cdev, NETIF_MSG_INTR, "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id); if (IS_PF(p_hwfn->cdev)) { p_ptt = qed_ptt_acquire(p_hwfn); if (!p_ptt) return -EBUSY; rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr, sb_phy_addr, rel_sb_id); qed_ptt_release(p_hwfn, p_ptt); } else { rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr, sb_phy_addr, rel_sb_id); } return rc; } static u32 qed_sb_release(struct qed_dev *cdev, struct qed_sb_info *sb_info, u16 sb_id, enum qed_sb_type type) { struct qed_hwfn *p_hwfn; u16 rel_sb_id; u32 rc; /* RoCE/Storage use a single engine in CMT mode while L2 uses both */ if (type == QED_SB_TYPE_L2_QUEUE) { p_hwfn = &cdev->hwfns[sb_id % cdev->num_hwfns]; rel_sb_id = sb_id / cdev->num_hwfns; } else { p_hwfn = QED_AFFIN_HWFN(cdev); rel_sb_id = sb_id; } DP_VERBOSE(cdev, NETIF_MSG_INTR, "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", IS_LEAD_HWFN(p_hwfn) ? 0 : 1, rel_sb_id, sb_id); rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id); return rc; } static bool qed_can_link_change(struct qed_dev *cdev) { return true; } static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) { struct qed_hwfn *hwfn; struct qed_mcp_link_params *link_params; struct qed_ptt *ptt; int rc; if (!cdev) return -ENODEV; /* The link should be set only once per PF */ hwfn = &cdev->hwfns[0]; /* When VF wants to set link, force it to read the bulletin instead. * This mimics the PF behavior, where a noitification [both immediate * and possible later] would be generated when changing properties. */ if (IS_VF(cdev)) { qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG); return 0; } ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EBUSY; link_params = qed_mcp_get_link_params(hwfn); if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) link_params->speed.autoneg = params->autoneg; if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { link_params->speed.advertised_speeds = 0; if (params->adv_speeds & QED_LM_1000baseT_Full_BIT) link_params->speed.advertised_speeds |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G; if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT) link_params->speed.advertised_speeds |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; if (params->adv_speeds & QED_LM_20000baseKR2_Full_BIT) link_params->speed.advertised_speeds |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G; if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT) link_params->speed.advertised_speeds |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT) link_params->speed.advertised_speeds |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G; if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT) link_params->speed.advertised_speeds |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT) link_params->speed.advertised_speeds |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; } if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) link_params->speed.forced_speed = params->forced_speed; if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) link_params->pause.autoneg = true; else link_params->pause.autoneg = false; if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) link_params->pause.forced_rx = true; else link_params->pause.forced_rx = false; if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) link_params->pause.forced_tx = true; else link_params->pause.forced_tx = false; } #ifndef QED_UPSTREAM if (loopback_mode && !(params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE)) { params->override_flags |= QED_LINK_OVERRIDE_LOOPBACK_MODE; params->loopback_mode = loopback_mode; } #endif if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) { switch (params->loopback_mode) { case QED_LINK_LOOPBACK_INT_PHY: link_params->loopback_mode = ETH_LOOPBACK_INT_PHY; break; case QED_LINK_LOOPBACK_EXT_PHY: link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY; break; case QED_LINK_LOOPBACK_EXT: link_params->loopback_mode = ETH_LOOPBACK_EXT; break; case QED_LINK_LOOPBACK_MAC: link_params->loopback_mode = ETH_LOOPBACK_MAC; break; case QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123: link_params->loopback_mode = ETH_LOOPBACK_CNIG_AH_ONLY_0123; break; case QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301: link_params->loopback_mode = ETH_LOOPBACK_CNIG_AH_ONLY_2301; break; case QED_LINK_LOOPBACK_PCS_AH_ONLY: link_params->loopback_mode = ETH_LOOPBACK_PCS_AH_ONLY; break; case QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY: link_params->loopback_mode = ETH_LOOPBACK_REVERSE_MAC_AH_ONLY; break; case QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY: link_params->loopback_mode = ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY; break; default: link_params->loopback_mode = ETH_LOOPBACK_NONE; break; } } if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG) memcpy(&link_params->eee, ¶ms->eee, sizeof(link_params->eee)); /* TODO - override default values */ rc = qed_mcp_set_link(hwfn, ptt, params->link_up); qed_ptt_release(hwfn, ptt); return rc; } static int qed_get_port_type(u32 media_type) { int port_type; switch (media_type) { case MEDIA_SFPP_10G_FIBER: case MEDIA_SFP_1G_FIBER: case MEDIA_XFP_FIBER: case MEDIA_MODULE_FIBER: case MEDIA_KR: port_type = PORT_FIBRE; break; case MEDIA_DA_TWINAX: port_type = PORT_DA; break; case MEDIA_BASE_T: port_type = PORT_TP; break; case MEDIA_NOT_PRESENT: port_type = PORT_NONE; break; case MEDIA_UNSPECIFIED: default: port_type = PORT_OTHER; break; } return port_type; } static void qed_fill_link_capability(struct qed_hwfn *hwfn, struct qed_ptt *ptt, u32 capability, u32 *if_capability) { u32 media_type, transceiver_data, tcvr_type; u32 speed_mask, board_cfg; qed_mcp_get_media_type(hwfn, ptt, &media_type); qed_mcp_get_transceiver_data(hwfn, ptt, &transceiver_data); qed_mcp_trans_speed_mask(hwfn, ptt, &speed_mask); qed_mcp_get_board_config(hwfn, ptt, &board_cfg); tcvr_type = GET_MFW_FIELD(transceiver_data, ETH_TRANSCEIVER_TYPE); switch (media_type) { case MEDIA_DA_TWINAX: /* DAC */ if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) *if_capability |= QED_LM_20000baseKR2_Full_BIT; /* For DAC media multiple speed capabilities are supported*/ capability = capability & speed_mask; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) *if_capability |= QED_LM_1000baseKX_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) *if_capability |= QED_LM_10000baseCR_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) *if_capability |= QED_LM_40000baseCR4_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) *if_capability |= QED_LM_25000baseCR_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) *if_capability |= QED_LM_50000baseCR2_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) *if_capability |= QED_LM_100000baseCR4_Full_BIT; break; case MEDIA_BASE_T: if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) { if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) { *if_capability |= QED_LM_1000baseT_Full_BIT; } if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) { *if_capability |= QED_LM_10000baseT_Full_BIT; } } if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) { if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET) *if_capability |= QED_LM_1000baseT_Full_BIT; if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET) *if_capability |= QED_LM_10000baseT_Full_BIT; } break; case MEDIA_SFP_1G_FIBER: case MEDIA_SFPP_10G_FIBER: case MEDIA_XFP_FIBER: case MEDIA_MODULE_FIBER: /* optical*/ if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) { if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) || (tcvr_type == ETH_TRANSCEIVER_TYPE_1G_SX)) *if_capability |= QED_LM_1000baseKX_Full_BIT; } if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) { if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_SR) *if_capability |= QED_LM_10000baseSR_Full_BIT; if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LR) *if_capability |= QED_LM_10000baseLR_Full_BIT; if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LRM) *if_capability |= QED_LM_10000baseLRM_Full_BIT; if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_ER) *if_capability |= QED_LM_10000baseR_FEC_BIT; } if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) *if_capability |= QED_LM_20000baseKR2_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) { if (tcvr_type == ETH_TRANSCEIVER_TYPE_25G_SR) *if_capability |= QED_LM_25000baseSR_Full_BIT; } if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) { if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_LR4) *if_capability |= QED_LM_40000baseLR4_Full_BIT; if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_SR4) *if_capability |= QED_LM_40000baseSR4_Full_BIT; } if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) *if_capability |= QED_LM_50000baseKR2_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) { if (tcvr_type == ETH_TRANSCEIVER_TYPE_100G_SR4) *if_capability |= QED_LM_100000baseSR4_Full_BIT; } break; case MEDIA_KR: if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) *if_capability |= QED_LM_20000baseKR2_Full_BIT; /* For KR media multiple speed capabilities are supported*/ capability = capability & speed_mask; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) *if_capability |= QED_LM_1000baseKX_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) *if_capability |= QED_LM_10000baseKR_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) *if_capability |= QED_LM_25000baseKR_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) *if_capability |= QED_LM_40000baseKR4_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) *if_capability |= QED_LM_50000baseKR2_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) *if_capability |= QED_LM_100000baseKR4_Full_BIT; break; case MEDIA_UNSPECIFIED: case MEDIA_NOT_PRESENT: DP_VERBOSE(hwfn->cdev, QED_MSG_DEBUG, "Unknown media and transceiver type;\n"); break; } } static void qed_fill_link(struct qed_hwfn *hwfn, struct qed_ptt *ptt, struct qed_link_output *if_link) { struct qed_mcp_link_capabilities link_caps; struct qed_mcp_link_params params; struct qed_mcp_link_state link; u32 media_type; memset(if_link, 0, sizeof(*if_link)); /* Prepare source inputs */ if (IS_PF(hwfn->cdev)) { memcpy(¶ms, qed_mcp_get_link_params(hwfn), sizeof(params)); memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link)); memcpy(&link_caps, qed_mcp_get_link_capabilities(hwfn), sizeof(link_caps)); } else { qed_vf_get_link_params(hwfn, ¶ms); qed_vf_get_link_state(hwfn, &link); qed_vf_get_link_caps(hwfn, &link_caps); } /* Set the link parameters to pass to protocol driver */ if (link.link_up) if_link->link_up = true; /* TODO - at the moment assume supported and advertised speed equal */ if_link->supported_caps = QED_LM_FIBRE_BIT; if (link_caps.default_speed_autoneg) if_link->supported_caps |= QED_LM_Autoneg_BIT; if (params.pause.autoneg || (params.pause.forced_rx && params.pause.forced_tx)) if_link->supported_caps |= QED_LM_Asym_Pause_BIT; if (params.pause.autoneg || params.pause.forced_rx || params.pause.forced_tx) if_link->supported_caps |= QED_LM_Pause_BIT; if_link->advertised_caps = if_link->supported_caps; if (params.speed.autoneg) if_link->advertised_caps |= QED_LM_Autoneg_BIT; else if_link->advertised_caps &= ~QED_LM_Autoneg_BIT; /* Fill link advertised capability*/ qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds, &if_link->advertised_caps); /* Fill link supported capability*/ qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities, &if_link->supported_caps); if (link.link_up) if_link->speed = link.speed; /* TODO - fill duplex properly */ if_link->duplex = DUPLEX_FULL; qed_mcp_get_media_type(hwfn, ptt, &media_type); if_link->port = qed_get_port_type(media_type); if_link->autoneg = params.speed.autoneg; if (params.pause.autoneg) if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; if (params.pause.forced_rx) if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; if (params.pause.forced_tx) if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; /* Link partner capabilities */ if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD) if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_20G) if_link->lp_caps |= QED_LM_20000baseKR2_Full_BIT; if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; if (link.an_complete) if_link->lp_caps |= QED_LM_Autoneg_BIT; if (link.partner_adv_pause) if_link->lp_caps |= QED_LM_Pause_BIT; if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) if_link->lp_caps |= QED_LM_Asym_Pause_BIT; if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) { if_link->eee_supported = false; } else { if_link->eee_supported = true; if_link->eee_active = link.eee_active; if_link->sup_caps = link_caps.eee_speed_caps; /* MFW clears adv_caps on eee disable; use configured value */ if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps : params.eee.adv_caps; if_link->eee.lp_adv_caps = link.eee_lp_adv_caps; if_link->eee.enable = params.eee.enable; if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable; if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer; } } static void qed_get_current_link(struct qed_dev *cdev, struct qed_link_output *if_link) { struct qed_hwfn *hwfn; struct qed_ptt *ptt; int i; hwfn = &cdev->hwfns[0]; if (IS_PF(cdev)) { ptt = qed_ptt_acquire(hwfn); if (!ptt) DP_NOTICE(hwfn, "Failed to fill link; No PTT\n"); qed_fill_link(hwfn, ptt, if_link); if (ptt) qed_ptt_release(hwfn, ptt); } else { qed_fill_link(hwfn, NULL, if_link); } for_each_hwfn(cdev, i) qed_inform_vf_link_state(&cdev->hwfns[i]); } void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt) { void *cookie = hwfn->cdev->ops_cookie; struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common; struct qed_link_output if_link; qed_fill_link(hwfn, ptt, &if_link); qed_inform_vf_link_state(hwfn); if (IS_LEAD_HWFN(hwfn) && cookie) op->link_update(cookie, &if_link); } static int qed_drain(struct qed_dev *cdev) { struct qed_hwfn *hwfn; struct qed_ptt *ptt; int i, rc; if (IS_VF(cdev)) return 0; for_each_hwfn(cdev, i) { hwfn = &cdev->hwfns[i]; ptt = qed_ptt_acquire(hwfn); if (!ptt) { DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n"); return -EBUSY; } rc = qed_mcp_drain(hwfn, ptt); if (rc) return rc; qed_ptt_release(hwfn, ptt); } return 0; } static int qed_nvm_get_cmd(struct qed_dev *cdev, u32 cmd, u32 addr, u8 *buf, u32 len) { int rc = 0; switch (cmd) { case QED_NVM_READ_NVRAM: rc = qed_mcp_nvm_read(cdev, addr, buf, len); break; case QED_GET_MCP_NVM_RESP: rc = qed_mcp_nvm_resp(cdev, buf); break; default: rc = -EOPNOTSUPP; cdev->mcp_nvm_resp = FW_MSG_CODE_NVM_OPERATION_FAILED; DP_NOTICE(cdev, "Unknown command %d\n", cmd); break; } return rc; } static int qed_nvm_set_cmd(struct qed_dev *cdev, u32 cmd, u32 addr, u8 *buf, u32 len) { int rc = 0; switch (cmd) { case QED_NVM_DEL_FILE: rc = qed_mcp_nvm_del_file(cdev, addr); break; case QED_PUT_FILE_BEGIN: rc = qed_mcp_nvm_put_file_begin(cdev, addr); break; case QED_PUT_FILE_DATA: case QED_NVM_WRITE_NVRAM: case QED_EXT_PHY_FW_UPGRADE: case QED_ENCRYPT_PASSWORD: rc = qed_mcp_nvm_write(cdev, cmd, addr, buf, len); break; default: rc = -EOPNOTSUPP; cdev->mcp_nvm_resp = FW_MSG_CODE_NVM_OPERATION_FAILED; DP_NOTICE(cdev, "Unknown command 0x%x\n", cmd); break; } return rc; } static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, u8 *buf, u16 len) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); struct qed_ptt *ptt = qed_ptt_acquire(hwfn); int rc; if (!ptt) return -EAGAIN; rc = qed_mcp_get_nvm_image(hwfn, ptt, type, buf, len); qed_ptt_release(hwfn, ptt); return rc; } void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn) { struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common; void *cookie = p_hwfn->cdev->ops_cookie; if (ops) ops->schedule_recovery_handler(cookie); } void qed_hw_error_occurred(struct qed_hwfn *p_hwfn, enum qed_hw_err_type err_type) { struct qed_common_cb_ops *ops = p_hwfn->cdev->protocol_ops.common; void *cookie = p_hwfn->cdev->ops_cookie; char err_str[32]; switch (err_type) { case QED_HW_ERR_FAN_FAIL: strcpy(err_str, "Fan Failure"); break; case QED_HW_ERR_MFW_RESP_FAIL: strcpy(err_str, "MFW Response Failure"); break; case QED_HW_ERR_HW_ATTN: strcpy(err_str, "HW Attention"); break; case QED_HW_ERR_DMAE_FAIL: strcpy(err_str, "DMAE Failure"); break; case QED_HW_ERR_RAMROD_FAIL: strcpy(err_str, "Ramrod Failure"); break; case QED_HW_ERR_FW_ASSERT: strcpy(err_str, "FW Assertion"); break; default: strcpy(err_str, "Unknown"); break; } DP_NOTICE(p_hwfn, "HW error occurred [%s]\n", err_str); /* Call the HW error handler of the protocol driver. * If it is not available - perform a minimal handling of preventing * HW attentions from being reasserted. */ if (ops) ops->schedule_hw_err_handler(cookie, err_type); else qed_int_attn_clr_enable(p_hwfn->cdev, true); } static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal) { *rx_coal = cdev->rx_coalesce_usecs; *tx_coal = cdev->tx_coalesce_usecs; } static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, void *handle) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); return qed_set_queue_coalesce(hwfn, rx_coal, tx_coal, handle); } static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); struct qed_ptt *ptt; int status = 0; ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EAGAIN; status = qed_mcp_set_led(hwfn, ptt, mode); qed_ptt_release(hwfn, ptt); return status; } static int qed_recovery_process(struct qed_dev *cdev) { struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); struct qed_ptt *p_ptt; int rc = 0; p_ptt = qed_ptt_acquire(p_hwfn); if (!p_ptt) return -EAGAIN; rc = qed_start_recovery_process(p_hwfn, p_ptt); qed_ptt_release(p_hwfn, p_ptt); return rc; } static int qed_update_wol(struct qed_dev *cdev, bool enabled) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); struct qed_ptt *ptt; int rc = 0; if (IS_VF(cdev)) return 0; ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EAGAIN; rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED : QED_OV_WOL_DISABLED); if (rc) goto out; rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); out: qed_ptt_release(hwfn, ptt); return rc; } static int qed_update_drv_state(struct qed_dev *cdev, bool active) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); struct qed_ptt *ptt; int status = 0; if (IS_VF(cdev)) return 0; ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EAGAIN; status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ? QED_OV_DRIVER_STATE_ACTIVE : QED_OV_DRIVER_STATE_DISABLED); qed_ptt_release(hwfn, ptt); return status; } static int qed_update_mac(struct qed_dev *cdev, u8 *mac) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); struct qed_ptt *ptt; int status = 0; if (IS_VF(cdev)) return 0; ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EAGAIN; status = qed_mcp_ov_update_mac(hwfn, ptt, mac); if (status) goto out; status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); out: qed_ptt_release(hwfn, ptt); return status; } static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); struct qed_ptt *ptt; int status = 0; if (IS_VF(cdev)) return 0; ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EAGAIN; status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu); if (status) goto out; status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV); out: qed_ptt_release(hwfn, ptt); return status; } static int qed_get_sb_info(struct qed_dev *cdev, struct qed_sb_info *sb, u16 qid, struct qed_sb_info_dbg *sb_dbg) { struct qed_hwfn *hwfn = &cdev->hwfns[qid % cdev->num_hwfns]; struct qed_ptt *ptt; int rc; if (IS_VF(cdev)) return -EINVAL; ptt = qed_ptt_acquire(hwfn); if (!ptt) { DP_NOTICE(hwfn, "Can't acquire PTT\n"); return -EAGAIN; } memset(sb_dbg, 0, sizeof(*sb_dbg)); rc = qed_int_get_sb_dbg(hwfn, ptt, sb, sb_dbg); qed_ptt_release(hwfn, ptt); return rc; } static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf, u32 offset, u32 len) { struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); u32 port = hwfn->port_id; struct qed_ptt *ptt; int rc = 0; if (IS_VF(cdev)) return 0; ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EAGAIN; rc = qed_mcp_phy_sfp_read(hwfn, ptt, port, I2C_TRANSCEIVER_ADDR, offset, len, buf); qed_ptt_release(hwfn, ptt); return rc; } static int qed_get_sfp_stats(struct qed_dev *cdev, struct qed_sfp_stats *sfp) { u32 vcc, txb, txp, rxp, temp, addr, len, media; struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev); u8 lane, buf[64], port = hwfn->port_id; struct qed_ptt *ptt; int rc, i; ptt = qed_ptt_acquire(hwfn); if (!ptt) return -EAGAIN; qed_mcp_get_media_type(hwfn, ptt, &media); if (media == MEDIA_UNSPECIFIED || media == MEDIA_NOT_PRESENT) { DP_ERR(cdev, "Unknown media type 0x%x\n", media); rc = -EINVAL; goto out; } memset(&buf, 0, sizeof(buf)); memset(sfp, 0, sizeof(*sfp)); rc = qed_mcp_phy_sfp_read(hwfn, ptt, port, I2C_TRANSCEIVER_ADDR, 0, 1, buf); if (rc) goto out; sfp->sfp_type = buf[0]; switch (sfp->sfp_type) { case 0x3: /* SFP, SFP+, SFP-28 */ len = 0xa; lane = 1; addr = I2C_DEV_ADDR_A2; temp = SFP_EEPROM_A2_TEMPERATURE_ADDR; vcc = SFP_EEPROM_A2_VCC_ADDR - temp; txb = SFP_EEPROM_A2_TX_BIAS_ADDR - temp; txp = SFP_EEPROM_A2_TX_POWER_ADDR - temp; rxp = SFP_EEPROM_A2_RX_POWER_ADDR - temp; break; case 0xc: /* QSFP */ case 0xd: /* QSFP+ */ case 0x11: /* QSFP-28 */ len = 0x24; lane = 4; addr = I2C_DEV_ADDR_A0; temp = QSFP_EEPROM_A0_TEMPERATURE_ADDR; vcc = QSFP_EEPROM_A0_VCC_ADDR - temp; txb = QSFP_EEPROM_A0_TX1_BIAS_ADDR - temp; txp = QSFP_EEPROM_A0_TX1_POWER_ADDR - temp; rxp = QSFP_EEPROM_A0_RX1_POWER_ADDR - temp; break; case 0x12: /* CXP2 (CXP-28) */ default: DP_ERR(cdev, "SFP type 0x%x not supported\n", sfp->sfp_type); rc = -EINVAL; goto out; } /* Read temperature */ rc = qed_mcp_phy_sfp_read(hwfn, ptt, port, addr, temp, len, buf); if (rc) goto out; memcpy((u8 *)&sfp->temperature, buf, 2); memcpy((u8 *)&sfp->vcc, (buf + vcc), 2); for (i = 0; i < lane; i++) { memcpy((u8 *)&sfp->lane[i].rx_power, (buf + (rxp + i * 2)), 2); memcpy((u8 *)&sfp->lane[i].tx_bias, (buf + (txb + i * 2)), 2); memcpy((u8 *)&sfp->lane[i].tx_power, (buf + (txp + i * 2)), 2); } out: qed_ptt_release(hwfn, ptt); return rc; } static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev) { return QED_AFFIN_HWFN_IDX(cdev); } static struct qed_selftest_ops qed_selftest_ops_pass = { INIT_STRUCT_FIELD(selftest_memory, &qed_selftest_memory), INIT_STRUCT_FIELD(selftest_interrupt, &qed_selftest_interrupt), INIT_STRUCT_FIELD(selftest_register, &qed_selftest_register), INIT_STRUCT_FIELD(selftest_clock, &qed_selftest_clock), INIT_STRUCT_FIELD(selftest_nvram, &qed_selftest_nvram), }; extern const struct qed_dcbnl_ops qed_dcbnl_ops_pass; const struct qed_common_ops qed_common_ops_pass = { INIT_STRUCT_FIELD(selftest, &qed_selftest_ops_pass), INIT_STRUCT_FIELD(dcb, &qed_dcbnl_ops_pass), INIT_STRUCT_FIELD(probe, &qed_probe), INIT_STRUCT_FIELD(remove, &qed_remove), INIT_STRUCT_FIELD(set_power_state, &qed_set_power_state), INIT_STRUCT_FIELD(set_name, &qed_set_name), INIT_STRUCT_FIELD(get_dev_name, &qed_get_dev_name), INIT_STRUCT_FIELD(update_pf_params, &qed_update_pf_params), INIT_STRUCT_FIELD(slowpath_start, &qed_slowpath_start), INIT_STRUCT_FIELD(slowpath_stop, &qed_slowpath_stop), INIT_STRUCT_FIELD(set_fp_int, &qed_set_int_fp), INIT_STRUCT_FIELD(get_fp_int, &qed_get_int_fp), INIT_STRUCT_FIELD(sb_init, &qed_sb_init), INIT_STRUCT_FIELD(sb_release, &qed_sb_release), INIT_STRUCT_FIELD(get_sb_info, &qed_get_sb_info), INIT_STRUCT_FIELD(simd_handler_config, &qed_simd_handler_config), INIT_STRUCT_FIELD(simd_handler_clean, &qed_simd_handler_clean), INIT_STRUCT_FIELD(can_link_change, &qed_can_link_change), INIT_STRUCT_FIELD(set_link, &qed_set_link), INIT_STRUCT_FIELD(get_link, &qed_get_current_link), INIT_STRUCT_FIELD(drain, &qed_drain), INIT_STRUCT_FIELD(update_msglvl, &qed_init_dp), #ifdef CONFIG_DEBUG_FS INIT_STRUCT_FIELD(dbg_grc, &qed_dbg_grc), INIT_STRUCT_FIELD(dbg_grc_size, &qed_dbg_grc_size), INIT_STRUCT_FIELD(dbg_idle_chk, &qed_dbg_idle_chk), INIT_STRUCT_FIELD(dbg_idle_chk_size, &qed_dbg_idle_chk_size), INIT_STRUCT_FIELD(dbg_mcp_trace, &qed_dbg_mcp_trace), INIT_STRUCT_FIELD(dbg_mcp_trace_size, &qed_dbg_mcp_trace_size), INIT_STRUCT_FIELD(dbg_protection_override, &qed_dbg_protection_override), INIT_STRUCT_FIELD(dbg_protection_override_size, &qed_dbg_protection_override_size), INIT_STRUCT_FIELD(dbg_reg_fifo, &qed_dbg_reg_fifo), INIT_STRUCT_FIELD(dbg_reg_fifo_size, &qed_dbg_reg_fifo_size), INIT_STRUCT_FIELD(dbg_igu_fifo, &qed_dbg_igu_fifo), INIT_STRUCT_FIELD(dbg_igu_fifo_size, &qed_dbg_igu_fifo_size), INIT_STRUCT_FIELD(dbg_phy, &qed_dbg_phy), INIT_STRUCT_FIELD(dbg_phy_size, &qed_dbg_phy_size), INIT_STRUCT_FIELD(dbg_fw_asserts, &qed_dbg_fw_asserts), INIT_STRUCT_FIELD(dbg_fw_asserts_size, &qed_dbg_fw_asserts_size), INIT_STRUCT_FIELD(dbg_get_debug_engine, &qed_get_debug_engine), INIT_STRUCT_FIELD(dbg_set_debug_engine, &qed_set_debug_engine), INIT_STRUCT_FIELD(dbg_all_data, &qed_dbg_all_data), INIT_STRUCT_FIELD(dbg_all_data_size, &qed_dbg_all_data_size), INIT_STRUCT_FIELD(dbg_save_all_data, &qed_dbg_save_all_data), #endif INIT_STRUCT_FIELD(chain_alloc, &qed_chain_alloc), INIT_STRUCT_FIELD(chain_free, &qed_chain_free), INIT_STRUCT_FIELD(chain_print, &qed_chain_print), INIT_STRUCT_FIELD(nvm_get_cmd, &qed_nvm_get_cmd), INIT_STRUCT_FIELD(nvm_set_cmd, &qed_nvm_set_cmd), INIT_STRUCT_FIELD(nvm_get_image, &qed_nvm_get_image), INIT_STRUCT_FIELD(get_coalesce, &qed_get_coalesce), INIT_STRUCT_FIELD(set_coalesce, &qed_set_coalesce), INIT_STRUCT_FIELD(set_led, &qed_set_led), INIT_STRUCT_FIELD(recovery_process, &qed_recovery_process), INIT_STRUCT_FIELD(recovery_prolog, &qed_recovery_prolog), INIT_STRUCT_FIELD(attn_clr_enable, &qed_int_attn_clr_enable), INIT_STRUCT_FIELD(update_drv_state, &qed_update_drv_state), INIT_STRUCT_FIELD(update_mac, &qed_update_mac), INIT_STRUCT_FIELD(update_mtu, &qed_update_mtu), INIT_STRUCT_FIELD(update_wol, &qed_update_wol), INIT_STRUCT_FIELD(db_recovery_add, &qed_db_recovery_add), INIT_STRUCT_FIELD(db_recovery_del, &qed_db_recovery_del), INIT_STRUCT_FIELD(read_module_eeprom, &qed_read_module_eeprom), INIT_STRUCT_FIELD(get_vport_stats, &qed_get_vport_stats), INIT_STRUCT_FIELD(get_sfp_stats, &qed_get_sfp_stats), INIT_STRUCT_FIELD(get_affin_hwfn_idx, &qed_get_affin_hwfn_idx), }; const struct qed_lag_ops qed_lag_ops_pass = { INIT_STRUCT_FIELD(lag_create, &qed_lag_create), INIT_STRUCT_FIELD(lag_modify, &qed_lag_modify), INIT_STRUCT_FIELD(lag_destroy, &qed_lag_destroy), }; #ifndef QED_UPSTREAM u32 qed_get_protocol_version(enum qed_protocol protocol) { switch (protocol) { case QED_PROTOCOL_ETH: return QED_ETH_INTERFACE_VERSION; case QED_PROTOCOL_FCOE: return QED_FCOE_INTERFACE_VERSION; case QED_PROTOCOL_ISCSI: return QED_ISCSI_INTERFACE_VERSION; default: return 0; } } EXPORT_SYMBOL(qed_get_protocol_version); #endif #ifdef CONFIG_QED_RDMA static void qed_get_roce_stats(struct qed_dev *cdev, struct qed_rdma_stats_out_params *stats) { int rc; if (!cdev) { memset(stats, 0, sizeof(*stats)); return; } /* All RoCE stats are collected by the dedicated qed callback. If qedr * will add non qed functionality for collecting stats in the future we * should climb into qedr here, and allow that function to do its thing * and drop back into qed_rdma_query_stats() instead of invoking it * directly. * Currently RoCE uses only function 0. */ rc = qed_rdma_query_stats(&cdev->hwfns[0], 0 /* assume stats queue 0 */, stats); if (rc) memset(stats, 0, sizeof(*stats)); } #endif void qed_get_protocol_stats(struct qed_dev *cdev, enum qed_mcp_protocol_type type, union qed_mcp_protocol_stats *stats) { struct qed_eth_stats eth_stats; #ifdef CONFIG_QED_RDMA struct qed_rdma_stats_out_params roce_stats; #endif memset(stats, 0, sizeof(*stats)); /* TODO - all of this is ifdefs here are incorrect [protocol headers * should always be included and have empty implementation in case * protocol is left out]. But for now this is required as it allows * tedibear to compile [doesn't take anything but L2]. */ switch (type) { case QED_MCP_LAN_STATS: qed_get_vport_stats(cdev, ð_stats); stats->lan_stats.ucast_rx_pkts = eth_stats.common.rx_ucast_pkts; stats->lan_stats.ucast_tx_pkts = eth_stats.common.tx_ucast_pkts; /* @@@TBD - L2 driver doesn't have this info */ stats->lan_stats.fcs_err = -1; break; #ifdef CONFIG_QED_RDMA case QED_MCP_RDMA_STATS: qed_get_roce_stats(cdev, &roce_stats); stats->rdma_stats.rx_bytes = roce_stats.rcv_bytes; stats->rdma_stats.rx_pkts = roce_stats.rcv_pkts; stats->rdma_stats.tx_byts = roce_stats.sent_bytes; stats->rdma_stats.tx_pkts = roce_stats.sent_pkts; break; #endif case QED_MCP_FCOE_STATS: qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats); break; case QED_MCP_ISCSI_STATS: qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats); break; default: DP_ERR(cdev, "Invalid protocol type = %d\n", type); return; } } int qed_mfw_tlv_req(struct qed_hwfn *hwfn) { DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV, "Scheduling slowpath task [Flag: %d]\n", QED_SLOWPATH_MFW_TLV_REQ); smp_mb__before_atomic(); set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags); smp_mb__after_atomic(); queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0); return 0; } static void qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv) { struct qed_common_cb_ops *op = cdev->protocol_ops.common; struct qed_eth_stats_common *p_common; struct qed_generic_tlvs gen_tlvs; struct qed_eth_stats stats; int i; memset(&gen_tlvs, 0, sizeof(gen_tlvs)); op->get_generic_tlv_data(cdev->ops_cookie, &gen_tlvs); if (gen_tlvs.feat_flags & QED_TLV_IP_CSUM) tlv->flags.ipv4_csum_offload = true; if (gen_tlvs.feat_flags & QED_TLV_LSO) tlv->flags.lso_supported = true; tlv->flags.b_set = true; for (i = 0; i < QED_MFW_TLV_MAC_COUNT; i++) { if (is_valid_ether_addr(gen_tlvs.mac[i])) { ether_addr_copy(tlv->mac[i], gen_tlvs.mac[i]); tlv->mac_set[i] = true; } } qed_get_vport_stats(cdev, &stats); p_common = &stats.common; tlv->rx_frames = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts + p_common->rx_bcast_pkts; tlv->rx_frames_set = true; tlv->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes + p_common->rx_bcast_bytes; tlv->rx_bytes_set = true; tlv->tx_frames = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts + p_common->tx_bcast_pkts; tlv->tx_frames_set = true; tlv->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes + p_common->tx_bcast_bytes; tlv->rx_bytes_set = true; } int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type, union qed_mfw_tlv_data *tlv_buf) { struct qed_dev *cdev = hwfn->cdev; struct qed_common_cb_ops *ops = cdev->protocol_ops.common; /* TODO - temporary until Storage fills it [prevent break] */ if (!ops->get_protocol_tlv_data || !ops->get_generic_tlv_data) { DP_NOTICE(hwfn, "Can't collect TLV management info\n"); return -EINVAL; } switch (type) { case QED_MFW_TLV_GENERIC: qed_fill_generic_tlv_data(hwfn->cdev, &tlv_buf->generic); break; case QED_MFW_TLV_ETH: ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->eth); break; case QED_MFW_TLV_FCOE: ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->fcoe); break; case QED_MFW_TLV_ISCSI: ops->get_protocol_tlv_data(cdev->ops_cookie, &tlv_buf->iscsi); break; default: break; } return 0; } int qed_hw_attr_update(struct qed_hwfn *hwfn, enum qed_hw_info_change attr) { struct qed_dev *cdev = hwfn->cdev; struct qed_common_cb_ops *ops = cdev->protocol_ops.common; if (ops && ops->hw_attr_update) ops->hw_attr_update(cdev->ops_cookie, attr); return 0; } #ifdef _MISSING_CRC8_MODULE /* ! QED_UPSTREAM */ void qed_crc8_populate_msb(u8 table[CRC8_TABLE_SIZE], u8 polynomial) { int i, j; const u8 msbit = 0x80; u8 t = msbit; table[0] = 0; for (i = 1; i < CRC8_TABLE_SIZE; i *= 2) { t = (t << 1) ^ (t & msbit ? polynomial : 0); for (j = 0; j < i; j++) table[i+j] = table[j] ^ t; } } u8 qed_crc8(const u8 table[CRC8_TABLE_SIZE], u8 *pdata, size_t nbytes, u8 crc) { /* loop over the buffer data */ while (nbytes-- > 0) crc = table[(crc ^ *pdata++) & 0xff]; return crc; } #endif