/* QLogic (R)NIC Driver/Library
 * Copyright (c) 2015-2016  QLogic Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef _QEDR_COMPAT_H_
#define _QEDR_COMPAT_H_

#ifndef ROCE_V2_UDP_DPORT
#define ROCE_V2_UDP_DPORT	(4791)
#endif

#ifndef USHRT_MAX
#define USHRT_MAX       ((u16)(~0U))
#endif

#if !DEFINED_RDMA_AH_ATTR
#define rdma_ah_attr			ib_ah_attr

static inline void rdma_ah_set_path_bits(struct ib_ah_attr *attr,
					 u8 src_path_bits)
{
	attr->src_path_bits = src_path_bits;
}
#if DEFINE_IB_AH_ATTR_WITH_DMAC
static inline u8 *rdma_ah_retrieve_dmac(struct ib_ah_attr *attr)
{
	return attr->dmac;
}
#endif

static inline const struct ib_global_route
		*rdma_ah_read_grh(const struct ib_ah_attr *attr)
{
	return &attr->grh;
}

static inline u8 rdma_ah_get_port_num(const struct ib_ah_attr *attr)
{
	return attr->port_num;
}
#endif

#ifdef NOT_DEFINED_IOMMU_PRESENT
static inline bool iommu_present(struct bus_type *bus)
{
	return iommu_found();
}
#endif

#ifndef array_size
#define array_size(x)  (sizeof(x) / sizeof((x)[0]))
#endif

#if defined(_DEFINE_ETHER_ADDR_COPY)
static inline void ether_addr_copy(u8 *dst, const u8 *src)
{
#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
	*(u32 *)dst = *(const u32 *)src;
	*(u16 *)(dst + 4) = *(const u16 *)(src + 4);
#else
	u16 *a = (u16 *)dst;
	const u16 *b = (const u16 *)src;

	a[0] = b[0];
	a[1] = b[1];
	a[2] = b[2];
#endif
}
#endif

#if defined(_DEFINE_ETHER_ADDR_EQUAL)
static inline bool ether_addr_equal(const u8 *addr1, const u8 *addr2)
{
#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
	u32 fold = ((*(const u32 *)addr1) ^ (*(const u32 *)addr2)) |
		   ((*(const u16 *)(addr1 + 4)) ^ (*(const u16 *)(addr2 + 4)));

	return fold == 0;
#else
	const u16 *a = (const u16 *)addr1;
	const u16 *b = (const u16 *)addr2;

	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0;
#endif
}
#endif

#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP64
#define PCI_EXP_DEVCAP2_ATOMIC_COMP64	(1 << 8)
#endif
#ifndef PCI_EXP_DEVCAP2_ATOMIC_ROUTE
#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE		(1 << 6)
#endif
#ifndef PCI_EXP_DEVCTL2_ATOMIC_REQ
#define PCI_EXP_DEVCTL2_ATOMIC_REQ		(1 << 6)
#endif
#ifndef PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK	(1 << 7)
#endif

#ifdef NOT_DEFINED_IB_RDMA_WR
#define rdma_wr(_wr) (&(_wr->wr.rdma))
#endif

#ifdef NOT_DEFINED_IB_UD_WR
#define ud_wr(_wr) (&(_wr->wr.ud))
#endif

#ifdef NOT_DEFINED_IB_ATOMIC_WR
#define atomic_wr(_wr) (&(_wr->wr.atomic))
#endif

#if !DEFINE_PCIE_CAPABILITY_OPS
static inline int pcie_capability_read_word(struct pci_dev *dev, int pos,
					    u16 *val)
{
	int ret;

	*val = 0;
	if (pos & 1)
		return -EINVAL;

	ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);

	/* Reset *val to 0 if pci_read_config_word() fails, it may
	 * have been written as 0xFFFF if hardware error happens
	 * during pci_read_config_word().
	 */

	if (ret)
		*val = 0;
	return ret;
}

static inline int pcie_capability_read_dword(struct pci_dev *dev, int pos,
					     u32 *val)
{
	int ret;

	ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
	if (ret)
		*val = 0;
	return ret;
}

static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
					     u16 clear)
{
	int ret;
	u16 val;

	if (pos & 1)
		return -EINVAL;

	ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, &val);
	if (!ret) {
		val &= ~clear;
		ret = pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
	}

	return ret;
}

static inline int pcie_capability_set_word(struct pci_dev *dev,
					   int pos, u16 set)
{
	int ret;
	u16 val;

	if (pos & 1)
		return -EINVAL;

	ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, &val);
	if (!ret) {
		val |= set;
		ret = pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
	}

	return ret;
}
#endif

#ifndef IS_ENABLED
#define __ARG_PLACEHOLDER_1 0,
#define config_enabled(cfg) _config_enabled(cfg)
#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value)
#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0)
#define ___config_enabled(__ignored, val, ...) val
#define genl_dump_check_consistent(cb, user_hdr, family)
#define IS_ENABLED(option) \
	(config_enabled(option) || config_enabled(option##_MODULE))
#endif

#ifndef ETH_P_IBOE
#define ETH_P_IBOE		(0x8915)
#endif

#ifdef DEFINE_DATA_ACCESS_EXCEEDS_WORD_SIZE
static __always_inline void data_access_exceeds_word_size(void)
#ifdef __compiletime_warning
__compiletime_warning("data access exceeds word size and won't be atomic")
#endif
;

static __always_inline void data_access_exceeds_word_size(void)
{
}
#endif

#ifdef DEFINE_READ_ONCE
static __always_inline void __read_once_size(volatile void *p, void *res, int size)
{
	switch (size) {
	case 1: *(__u8 *)res = *(volatile __u8 *)p; break;
	case 2: *(__u16 *)res = *(volatile __u16 *)p; break;
	case 4: *(__u32 *)res = *(volatile __u32 *)p; break;
#ifdef CONFIG_64BIT
	case 8: *(__u64 *)res = *(volatile __u64 *)p; break;
#endif
	default:
		barrier();
		memcpy((void *)res, (const void *)p, size);
		data_access_exceeds_word_size();
		barrier();
	}
}

#define READ_ONCE(x) \
	({ typeof(x) __val; __read_once_size(&x, &__val, sizeof(__val)); __val; })

#endif

#ifndef IS_ENABLED
#define __ARG_PLACEHOLDER_1 0,
#define __take_second_arg(__ignored, val, ...) val
#define __is_defined(x)			___is_defined(x)
#define ___is_defined(val)		____is_defined(__ARG_PLACEHOLDER_##val)
#define ____is_defined(arg1_or_junk)	__take_second_arg(arg1_or_junk 1, 0)
#define IS_ENABLED(option)		__is_defined(option)
#endif

#endif