/******************************************************************************* NAME fpgaRegDefines.h SUMMARY header file for Zebulon/Rocket FPGA register access function VERSION %version: 1.01 % UPDATE DATE %date_modified: Jul 08 06:40 2011 % PROGRAMMER %created_by: Shawn Wang % Copyright 2009-2011 NetApp/LSI Corporation. All Rights Reserved. DESCRIPTION: This file has code to access FPGA register for Pikes Peak (Zebulon) / Soyuz (Rocket) RAID controller Zebulon/Rocket are basically the same FPGA NOTES: REFERENCE: *******************************************************************************/ #ifndef __FPGA_REGISTER_DEFINES_H__ #define __FPGA_REGISTER_DEFINES_H__ #define LSI_VENDOR_ID 0x1000 #define NETAPP_VENDOR_ID 0x1275 #define LSI_ZEBULON_FPGA_DEVICE_ID 0x7110 #define LSI_ZEBULON_FPGA_BAR1_OFFSET 0x10 #define LSI_ZEBULON_FPGA_BAR2_OFFSET 0x14 #define LSI_ZEBULON_FPGA_BAR1_LENGTH 0xD8 #define LSI_ZEBULON_FPGA_BAR2_LENGTH 0x80000 #define LSI_ROCKET_FPGA_UART_BASE 0x3F8 #define LSI_ROCKET_FPGA_UART_OFFSET 8 /*** UUT Type ***/ #define PIKESPEAK_ID 0x1E #define SOYUZ_ID 0x14 /*** Common FPGA Register Address Offset ***/ //#define FPGA_DIAGNOSTIC_STATUS_LED 0x00000000 #define FPGA_BOARD_ID 0x00000001 //Board ID Register #define CTRL_ESM_N_BIT 0x10 //#define CONT_POSN_BIT 0x80 // Slot Position, 0=slot 1, 1=slot 2. (MSB) #define FPGA_SEVEN_SEGMENT_DISPLAY_1 0x00000002 #define FPGA_SEVEN_SEGMENT_DISPLAY_2 0x00000003 #define FPGA_MISCELLANEOUS_CONTROL_1 0x00000004 //Miscellaneous Control 1 Register #define AUD_ALARM_EN_BIT 0x08 #define FPGA_MISCELLANEOUS_CONTROL_2 0x00000005 //Miscellaneous Control 2 Register #define I2C_RESET_BIT 0x01 #define RTR_PS_0_LED_BIT 0x02 #define RTR_PS_1_LED_BIT 0x04 #define STANDBY_LED_BIT 0x40 #define OVER_TEMP_LED_BIT 0x80 #define FPGA_MISCELLANEOUS_CONTROL_3 0x00000006 //Miscellaneous Control 3 Register #define DRST_MASK_BIT 0X01 #define EN_UP_BOOT_BIT 0x02 //#define DEBUG_LED_EN_BIT 0x04 #define LED_SYNC_BIT 0x08 #define FPGA_LEGACY_MISCELLANEOUS_INFORMATION_1 0x00000008 //Miscellaneous Information Register #define PWR_FAIL_BIT 0x01 #define PUSH_BTN_BIT 0x02 #define PWR_BY_BBU_N_BIT 0x04 #define ALT_RSTIN_BIT 0x08 #define CWT_FAULT_BIT 0x10 #define ALT_FW_RUNNING_BIT 0x20 #define MAIN_PWR_FAIL_BIT 0x40 #define HOST_PWR_GOOD_BIT 0X80 #define FPGA_CWT_PROTECT 0x00000009 #define FPGA_CWT_ENABLE 0x0000000A #define FPGA_CWT_KEY 0x0000000B #define FPGA_CWT_CONTROL 0x0000000C #define FPGA_GENERAL_PURPOSE 0x0000000D #define FPGA_SUBSYSTEM_ID 0x0000000E #define FPGA_CLEAR_ALTERNATE_INPLACE_INTERRUPT 0x0000000F #define FPGA_CLEAR_SUBSYSTEM_INTERRUPT 0x00000010 #define FPGA_CLEAR_ALTERNATE_RESET_IN_LATCH 0x00000011 //#define FPGA_CLEAR_ALTERNATE_NMI_IN_LATCH 0x00000012 #define FPGA_CLEAR_ALT_MSG_LATCH 0x00000012 #define FPGA_CLEAR_POWER_FAIL_LATCH 0x00000013 //#define FPGA_CLEAR_DIRECTED_RESET_LATCH 0x00000014 #define FPGA_CLEAR_ALARM_CANCEL_LATCH 0x00000017 #define FPGA_ENABLE_BATTERIES 0x00000018 #define FPGA_DISABLE_BATTERIES 0x00000019 #define FPGA_REVISION 0x0000001A #define FPGA_DEVICE_ID 0x0000001B #define FPGA_UART_CONTROL 0x0000001C // Not support in Rocket #define FPGA_CLEAR_THERMAL_LATCH 0x0000001D #define FPGA_CLEAR_MAIN_POWER_FAIL_LATCH0 0x0000001E #define FPGA_CLEAN_PUSH_BUTTON_LATCH 0x0000001F #define FPGA_NVSRAM_LOCK 0x00000020 #define FPGA_SET_DIRECTED_RESET_LATCH 0x00000022 //Set Directed Latch Register #define DIR_RST_SET_BIT 0x01 #define FPGA_MISCELLANEOUS_INFORMATION_1 0x00000024 //Redundant Miscellaneous Information Register #define PWR_FAIL_BIT 0x01 #define PUSH_BTN_BIT 0x02 #define PWR_BY_BBU_BIT 0x04 #define ALT_RSTIN_BIT 0x08 #define CWT_FAULT_BIT 0x10 #define ALT_FW_RUNNING_BIT 0x20 #define MAIN_PWR_FAIL_BIT 0x40 #define HOST_PWR_GOOD_BIT 0X80 #define FPGA_MISCELLANEOUS_INFORMATION_2 0x00000025 #define CONT_POSN_BIT 0x10 #define FPGA_ENCODED_WRITE 0x00000030 #define FPGA_PROTECTED_WRITE_1 0x00000031 #define ALT_RST_OUT_BIT 0x01 //#define ALT_NMI_BIT 0x02 //Unused in FPGA REV.08 #define TEST_MODE_EN_BIT 0x04 #define BOARD_RESET_BIT 0x10 #define PS_CONTROL_BIT 0x20 //#define NMI_OUT_EN_BIT 0x40 //Unused in FPGA REV.08 #define FW_RUNNING_BIT 0x80 #define FPGA_PROTECTED_WRITE_2 0x00000032 //Protected Write 2 Register #define FPGA_RECONFIG_BIT 0x01 #define EN_DISCH_BIT 0x02 #define FPGA_SHUT_OFF_PS_BIT 0x08 #define PSOC_RESET_BIT 0x10 // Zebulon #define PSOC_ISSP_RST_BIT 0x10 // Rocket #define DISABLE_PHY_BIT 0x20 #define RST_PCIE_QE8_L_BIT 0x40 // Zebulon #define QE8_CFG12_1FNCT_BIT 0x80 // Zebulon #define BE3_AUX_PWR_BIT 0x40 // Rocket #define BE3_RESET_BIT 0x80 // Rocket #define FPGA_PROTECTED_WRITE_3 0x00000033 //Protected Write 3 Register #define ETHERNET_RST_BIT 0x01 #define FPGA_RST_CPLD_BIT 0x02 #define BOBCAT_DBGM_BIT 0x04 #define PCIE_SWT_RST_BIT 0x08 // Zebullon #define CLUSTER_RST_BIT 0x08 // Rocket #define SAS2X36_RST_BIT 0x10 #define HOST_CARD_RST_BIT 0x20 #define HOST_CARD_PS_DISABLE_BIT 0x40 #define RST_FALCON_BIT 0x80 // Zebullon #define RST_MUSTANG_BIT 0x80 // Rocket #define FPGA_PROTECTED_WRITE_4 0x00000034 //Protected Write 4 Register #define ADR_EN_BIT 0x01 #if defined(CTRLER_PIKESPEAK) #define ICH_PWR_BTN_BIT 0x02 // Zebullon #define SLP_S3_BIT 0x04 // Zebullon #define CKE_FORCE_LOW_BIT 0x08 // Zebullon #define RST_ISATA_BIT 0x10 // Zebullon #else #define CKE_FORCE_LOW_BIT 0x02 // Rocket #define RST_ISATA_BIT 0x04 // Rocket #define MASK_MAIN_PF_BIT 0x08 // Rocket #endif #define FPGA_LED_PATTERN_INDEX 0x00000039 #define FPGA_LED_PATTERN_SEQUENCE 0x0000003A #define FPGA_LED_PATTERN_HIGHEST_STATE 0x0000003B #define FPGA_LED_PATTERN_DURATION 0x0000003C #define FPGA_LED_INDEX 0x0000003D #define FPGA_LED_PATTERN_SELECTION 0x0000003F #define FPGA_ALTERNATE_BOARD_ID 0x00000049 //Alternate Board ID Register #define ALT_CTRLR_ESM_N_BIT 0x10 #define FPGA_HOST_BOARD_ID 0x00000048 #define FPGA_MIDPLANE_MISCELLANEOUS 0x0000004D //Midplane Miscellaneous 1 Register #define CARD_IO_TEST_BIT 0x02 #define FPGA_ENABLE_QUICK_SWITCH 0x00000050 //Enable Quick Switch Register #define EN_LS_CROSS_BIT 0x01 #define EN_PAIRING_BIT 0x02 #define EN_LS_INTER_CON_BIT 0x04 #define FPGA_ALT_MSG_IN 0x00000052 #define FPGA_ALT_MSG_OUT 0x00000053 #define FPGA_I2C_CONTROL_1 0x00000054 //I2C Control 1 Register #define I2C_DATA_BIT 0x01 #define I2C_CLK_BIT 0x02 #define FPGA_I2C_CONTROL_2 0x00000056 //I2C Control 2 Register #define MDPL_BUS1_SEL_BIT 0x01 #define MDPL_BUS2_SEL_BIT 0x02 #define MDPL_BUS1_RST_BIT 0x04 #define MDPL_BUS2_RST_BIT 0x08 #define FPGA_I2C_STATUS 0x00000057 //I2C Status Register #define I2C1_READY_BIT 0x01 #define I2C2_READY_BIT 0x02 #define FPGA_ENCLOSURE_DEFINED_CONTROL_1 0x0000005A //Enclosure Defined Control 1 Regiaster #define SYS_DEF_LP1_D_BIT 0x01 #define SYS_DEF_LP2_D_BIT 0x02 #define SYS_DEF_LP3_D_BIT 0x04 #define SYS_DEF_LP4_D_BIT 0x08 #define SYS_DEF_LP5_D_BIT 0x10 #define SYS_DEF_LP6_D_BIT 0x20 #define SYS_DEF_LP7_D_BIT 0x40 #define FPGA_ENCLOSURE_DEFINED_CONTROL_2 0x0000005B //Enclosure Defined Control 2 Regiaster #define SYS_DEF_HP1_D_BIT 0x01 #define SYS_DEF_HP2_D_BIT 0x02 #define SYS_DEF_HP3_D_BIT 0x04 #define SYS_DEF_HP4_D_BIT 0x08 #define FPGA_ENCLOSURE_DEFINED_VALUE_1 0x0000005C //Enclosure Defined Value 1 Regiaster #define SYS_DEF_LP1_V_BIT 0x01 #define SYS_DEF_LP2_V_BIT 0x02 #define SYS_DEF_LP3_V_BIT 0x04 #define SYS_DEF_LP4_V_BIT 0x08 #define SYS_DEF_LP5_V_BIT 0x10 #define SYS_DEF_LP6_V_BIT 0x20 #define SYS_DEF_LP7_V_BIT 0x40 #define FPGA_ENCLOSURE_DEFINED_VALUE_2 0x0000005D //Enclosure Defined Value 2 Regiaster #define SYS_DEF_HP1_V_BIT 0x01 #define SYS_DEF_HP2_V_BIT 0x02 #define SYS_DEF_HP3_V_BIT 0x04 #define SYS_DEF_HP4_V_BIT 0x08 #define FPGA_DRIVE_INPLACE_0 0x00000060 #define FPGA_DRIVE_INPLACE_1 0x00000061 #define FPGA_DRIVE_INPLACE_2 0x00000062 #define FPGA_SUBSYSTEM_STATUS_LINES_1 0x00000064 //Subsystem Status Lines 1 Register #define MAIN_PWR_FAIL_LATCH_BIT 0x01 #define PS_AC_GOOD_INT_BIT 0x02 #define PUSH_BTN_LT_BIT 0x20 #define FPGA_SUBSYSTEM_STATUS_LINES_2 0x00000065 //Subsystem Status Lines 2 Register #define PS0_FAULT_INT_BIT 0x01 #define PS1_FAULT_INT_BIT 0x02 #define CPU_TMP_INT_BIT 0x04 #define TMP_INT_BIT 0x08 #define ALARM_CANCEL_INT_BIT 0x20 #define PS0_OVER_TEMP_BIT 0x40 // Zebullon #define PS1_OVER_TEMP_BIT 0x80 // Zebullon #define FPGA_SUBSYSTEM_STATUS_LINES_3 0x00000066 //Subsystem Status Lines 3 Register #define PS0_INPL_BIT 0x01 #define PS1_INPL_BIT 0x02 #define BBU_INPL_BIT 0x04 #define ALT_INPL_BIT 0x08 #define HOTSWAT_PGOOD_BIT 0x10 // Zebullon #define BBU_EN_BIT 0x20 #define BOBCAT_RST_REQ_BIT 0x80 // Added since FPGA REV.08 #define FPGA_INTERRUPT_SOURCE_INT_A 0x00000070 #define FPGA_INTERRUPT_SOURCE_INT_B 0x00000071 //Interrupt Source INT_B Register #define SUBSYS_INT_BIT 0x01 #define I2C_INT_BIT 0x02 #define WDT_INT_BIT 0x04 #define ALT_MSG_INT_BIT 0x08 #define COB_UART_INT_BIT 0x10 //#define WDT_NMI_INT_BIT 0x04 //#define ALT_NMI_IN_BIT 0x08 #define FPGA_HIGH_PRIORITY_INTERRUPT_SOURCE 0x0000007C //Unused since FPGA REV.08 #define FPGA_SUBSYSTEM_INTERRUPT_MASK_1 0x00000084 //Subsystem Mask 1 #define MAIN_PWR_FAIL_MASK_BIT 0x01 #define PS_AC_GOOD_INT_MASK_BIT 0x02 #define PUSH_BTN_MASK_BIT 0x20 #define FPGA_SUBSYSTEM_INTERRUPT_MASK_2 0x00000085 //Subsystem Mask 2 #define PS0_FAULT_MASK_BIT 0x01 #define PS1_FAULT_MASK_BIT 0x02 #define CPU_TMP_MASK_BIT 0x04 #define TMP_MASK_BIT 0x08 #define ALARM_CANCEL_MASK_BIT 0x20 #define PS0_OVER_TEMP_MASK_BIT 0x40 // Zebullon #define PS1_OVER_TEMP_MASK_BIT 0x80 // Zebullon #define FPGA_SUBSYSTEM_INTERRUPT_MASK_3 0x00000086 #define FPGA_INTERRUPT_MASK_A 0x00000090 //Subsystem Mask 3 #define PS0_INPL_MASK_BIT 0x01 #define PS1_INPL_MASK_BIT 0x02 #define BBU_INPL_MASK_BIT 0x04 #define ALT_INPL_MASK_BIT 0x08 #define HOTSWAT_PGOOD_MASK_BIT 0x10 // Zebullon #define BBU_ENABLE_MASK_BIT 0x20 #define BOBCAT_RST_REQ_MASK_BIT 0x80 #define FPGA_INTERRUPT_MASK_B 0x00000091 //Interrupt Mask B #define SUBSYS_MASK_BIT 0x01 #define I2C_MASK_BIT 0x02 #define WDT_INT_MASK_BIT 0x04 #define ALT_MSG_INT_MASK_BIT 0x08 #define FPGA_SEVEN_SEGMENT_BLINK_CONTROL 0x00000098 //Seven-segment Blink Control Register #define DISPLAY_MODE_BIT 0x40 #define INSERT_BLANK_BIT 0x80 #define FPGA_EPP_STATUS_PORT 0x000000C1 //EPP Status Port Register #define EPP_TIMEOUT_BIT 0x01 #define EPP_IRQ_BIT 0x04 #define EPP_FOLLOW_AR_BIT 0x10 #define EPP_FOLLOW_DR_BIT 0x20 #define EPP_DONE_BIT 0x40 #define EPP_BUSY_BIT 0x80 #define FPGA_EPP_CONTROL_PORT 0x000000C2 //EPP Control Port Register #define EPP_RESET_BIT 0x04 #define EPP_EN_IRQ_BIT 0x10 #define FPGA_EPP_DATA_PORT 0x000000C3 #define FPGA_EPP_ADDRESS_PORT 0x000000C4 #define FPGA_FPGA_PROGRAM_RXDATA 0x000000D0 #define FPGA_FPGA_PROGRAM_TXDATA 0x000000D1 #define FPGA_FPGA_PROGRAM_STATUS 0x000000D2 //FPGA Program Status Registerr #define ROE_BIT 0x08 #define TOE_BIT 0x10 #define TMT_BIT 0x20 #define TRDY_BIT 0x40 #define RRDY_BIT 0x80 #define FPGA_FPGA_PROGRAM_CONTROL 0x000000D3 //FPGA Program Control Register #define SSO_BIT 0x01 #define IROE_BIT 0x08 #define ITOE_BIT 0x10 #define ITRDY_BIT 0x40 #define IRRDY_BIT 0x80 #define FPGA_FPGA_PROGRAM_SLAVE_SELECT 0x000000D5 //FPGA Program Slave Select Register #define SS_DEV0_BIT 0x01 #endif //__FPGA_REGISTER_LIB_H__