/******************************************************************************* NAME fpgaBbuPsDiag.h SUMMARY header file for Zebulon fpga BBU and power supply function diagnostics VERSION %version: 1 % UPDATE DATE %date_modified: Apr 298 10:40 2009 % PROGRAMMER %created_by: Jim Tu % Copyright 2009 Quanta Corporation. All Rights Reserved. DESCRIPTION: This file has code to test BBU and power supply function of Zebulon fpga NOTES: REFERENCE: *******************************************************************************/ #ifndef __FPGA_BBU_PS_DIAG_H__ #define __FPGA_BBU_PS_DIAG_H__ /*** Diagnostics Flags ***/ #ifndef __FPGA_LOW_RESET_DIAG_H__ #define __FPGA_LOW_RESET_DIAG_H__ #define LOW_RESET_SEQ_NORMAL 0x00 #define LOW_RESET_SEQ_PCI_GOOD 0x10 #define LOW_RESET_SEQ_PCI_FAIL 0x11 #define LOW_RESET_SEQ_HOST_CARD_GOOD 0x20 #define LOW_RESET_SEQ_HOST_CARD_FAIL 0x21 #define LOW_RESET_SEQ_HOST_CARD_ENABLE_FAIL 0x22 #define LOW_RESET_DIAG_SEQ_RECORD_OFFSET 0x58 #define LOW_RESET_ENCODED_UINT8_0_LOCATION 0x59 #define LOW_RESET_ENCODED_UINT8_1_LOCATION 0x5A #define LOW_RESET_ENCODED_UINT8_2_LOCATION 0x5B #define LOW_RESET_ENCODED_PATTERN_0 0x75 #define LOW_RESET_ENCODED_PATTERN_1 0x4B #define LOW_RESET_ENCODED_PATTERN_2 0x19 #define BBU_SWITCH_ENCODE_UINT8_0_LOCATION 0x5D #define BBU_SWITCH_ENCODE_UINT8_1_LOCATION 0x5E #define BBU_SWITCH_STATUS_LOCATION 0x5F #define BBU_SWITCH_ENCODE_PATTERN_0 0x39 #define BBU_SWITCH_ENCODE_PATTERN_1 0xD1 #define BBU_SWITCH_STATUS_NORMAL 0x00 #define BBU_SWITCH_STATUS_TEST 0x10 #define BBU_SWITCH_STATUS_BOOT 0x11 #endif //__FPGA_LOW_RESET_DIAG_H__ /*** Current Threshold ***/ /*** 0x3A00 is about 800mA, so the scale is 1:13.793mA. ***/ #define MID_NORMAL_CURRENT_LB 0x2000 #define MID_NORMAL_CURRENT_UB 0x6500 #define MID_OFF_CURRENT_UB 0x0500 #define MID_CURRENT_MASK 0xFF00; /*** Export Function ***/ // Power Supply Control VOID fpgaPwrEngagement(BOOLEAN vccPs, BOOLEAN vccBbu); VOID fpgaPwrAltEngagement(BOOLEAN vccPsAlt); INT32 fpgaBbuPsDiag(VOID); INT32 fpgaHostCardPsDisableDiag(VOID); #endif //__FPGA_BBU_PS_DIAG_H__