/*******************************************************************************

NAME            fpgaResetDiag.h
SUMMARY         header file for Zebulon FPGA reset function diagnostics
VERSION         %version: 1 %
UPDATE DATE     %date_modified: May 3 18:00 2009 %
PROGRAMMER      %created_by:    Jim Tu %

        Copyright 2009 Quanta Corporation. All Rights Reserved.

DESCRIPTION:
        This file has code to test reset function of Zebulon FPGA

NOTES:

REFERENCE:

*******************************************************************************/

#ifndef __FPGA_RESET_DIAG_H__
#define __FPGA_RESET_DIAG_H__

#define FPGA_RESET_SEQ_NORMAL    				0x00
#define FPGA_RESET_SEQ_ALT_IN    				0x10
#define FPGA_RESET_SEQ_COMPONENT 				0x11
#define FPGA_RESET_SEQ_FINISH					0x12
#define FPGA_RESET_RESULT_GOOD					0x00

//Result Byte 1
#define FPGA_RESET_RESULT_MID_I2C_1_FAIL		0x01
#define FPGA_RESET_RESULT_MID_I2C_2_FAIL		0x02

#define FPGA_RESET_RESULT_BOARD_FAIL			0x08
#define FPGA_RESET_RESULT_PSOC_FAIL				0x10
#define FPGA_RESET_RESULT_ETHERNET_FAIL			0x20
#define FPGA_RESET_RESULT_I2C_MUX_FAIL			0x40
#define FPGA_RESET_RESULT_CPLD_FAIL				0x80

//Result Byte 2
#define FPGA_RESET_RESULT_DIRECT_FAIL			0x01
#define FPGA_RESET_RESULT_DIRECT_CLEAR_FAIL		0x02
#define FPGA_RESET_RESULT_SAS2IOC_FAIL			0x04
#define FPGA_RESET_RESULT_SAS2X36_FAIL			0x08
#define FPGA_RESET_RESULT_PCIE_SWITCH_FAIL		0x10
#define FPGA_RESET_RESULT_QE8_FAIL				0x20
#define FPGA_RESET_RESULT_ISATA_FAIL			0x40
#define FPGA_RESET_RESULT_DRST_MASK_FAIL		0x80

//Result Byte 3
#define FPGA_RESET_RESULT_ALT_RST_IN_FAIL		0x01
#define FPGA_RESET_RESULT_ALT_RST_OUT_FAIL		0x02
#define FPGA_RESET_RESULT_ALT_RST_CLEAR_FAIL	0x03  

#define FPGA_RESET_DIAG_SEQ_RECORD_OFFSET		0x0B
#define FPGA_RESET_ENCODED_UINT8_0_LOCATION		0x0C
#define FPGA_RESET_ENCODED_UINT8_1_LOCATION		0x0D
#define FPGA_RESET_ENCODED_UINT8_2_LOCATION		0x0E
#define FPGA_RESET_RESULT_OFFSET_1				0x86C
#define FPGA_RESET_RESULT_OFFSET_2				0x86D
#define FPGA_RESET_RESULT_OFFSET_3				0x86E
#define FPGA_RESET_RESULT_OFFSET_4				0x86F
#define FPGA_RESET_ENCODED_PATTERN_0			0x85
#define FPGA_RESET_ENCODED_PATTERN_1			0xC4
#define FPGA_RESET_ENCODED_PATTERN_2			0x3F

#define FPGA_RESET_BAR1_OFFSET					0x10

/***  Export Function  ***/
INT32   fpgaResetDiag(VOID);
INT32   fpgaQE8LowPowerDiag(VOID);
VOID 	fpgaClearDirectedReset(VOID);
VOID 	fpgaClearAlternateReset(VOID);
VOID 	fpgaAlternateControllerReset(BOOLEAN status);


#endif	//__FPGA_RESET_DIAG_H__