NDS32 Dependent Features
************************

The NDS32 processors family includes high-performance and low-power 32-bit processors for high-end to low-end.  GNU AS for NDS32 architectures supports NDS32 ISA version 3.  For detail about NDS32 instruction set, please see the AndeStar ISA User Manual which is available at http://www.andestech.com/en/index/index.htm

NDS32 Options
=============

The NDS32 configurations of GNU AS support these special options:

-O1
     Optimize for performance.

-Os
     Optimize for space.

-EL
     Produce little endian data output.

-EB
     Produce little endian data output.

-mpic
     Generate PIC.

-mno-fp-as-gp-relax
     Suppress fp-as-gp relaxation for this file.

-mb2bb-relax
     Back-to-back branch optimization.

-mno-all-relax
     Suppress all relaxation for this file.

-march=<arch name>
     Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.

-mbaseline=<baseline>
     Assemble for baseline <baseline> which could be v2, v3, v3m.

-mfpu-freg=FREG
     Specify a FPU configuration.

     0      8 SP /  4 DP registers

     1     16 SP /  8 DP registers

     2     32 SP / 16 DP registers

     3     32 SP / 32 DP registers

-mabi=ABI
     Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.

-m[no-]mac
     Enable/Disable Multiply instructions support.

-m[no-]div
     Enable/Disable Divide instructions support.

-m[no-]16bit-ext
     Enable/Disable 16-bit extension

-m[no-]dx-regs
     Enable/Disable d0/d1 registers

-m[no-]perf-ext
     Enable/Disable Performance extension

-m[no-]perf2-ext
     Enable/Disable Performance extension 2

-m[no-]string-ext
     Enable/Disable String extension

-m[no-]reduced-regs
     Enable/Disable Reduced Register configuration (GPR16) option

-m[no-]audio-isa-ext
     Enable/Disable AUDIO ISA extension

-m[no-]fpu-sp-ext
     Enable/Disable FPU SP extension

-m[no-]fpu-dp-ext
     Enable/Disable FPU DP extension

-m[no-]fpu-fma
     Enable/Disable FPU fused-multiply-add instructions

-mall-ext
     Turn on all extensions and instructions support

Syntax
======

Special Characters
------------------

Use # at column 1 and ! anywhere in the line except inside quotes.

Multiple instructions in a line are allowed though not recommended and should be separated by ;.

Assembler is not case-sensitive in general except user defined label. For example, jral F1 is different from jral f1 while it is the same as JRAL F1.

Register Names
--------------

General purpose registers (GPR)
     There are 32 32-bit general purpose registers $r0 to $r31.

Accumulators d0 and d1
     64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo.

Assembler reserved register $ta
     Register $ta ($r15) is reserved for assembler using.

Operating system reserved registers $p0 and $p1
     Registers $p0 ($r26) and $p1 ($r27) are used by operating system as scratch registers.

Frame pointer $fp
     Register $r28 is regarded as the frame pointer.

Global pointer
     Register $r29 is regarded as the global pointer.

Link pointer
     Register $r30 is regarded as the link pointer.

Stack pointer
     Register $r31 is regarded as the stack pointer.

Pseudo Instructions
-------------------

li rt5,imm32
     load 32-bit integer into register rt5.  sethi rt5,hi20(imm32) and then ori rt5,reg,lo12(imm32).

la rt5,var
     Load 32-bit address of var into register rt5.  sethi rt5,hi20(var) and then ori reg,rt5,lo12(var)

l.[bhw] rt5,var
     Load value of var into register rt5.  sethi $ta,hi20(var) and then l[bhw]i rt5,[$ta+lo12(var)]

l.[bh]s rt5,var
     Load value of var into register rt5.  sethi $ta,hi20(var) and then l[bh]si rt5,[$ta+lo12(var)]

l.[bhw]p rt5,var,inc
     Load value of var into register rt5 and increment $ta by amount inc. la $ta,var and then l[bhw]i.bi rt5,[$ta],inc

l.[bhw]pc rt5,inc
     Continue loading value of var into register rt5 and increment $ta by amount inc. l[bhw]i.bi rt5,[$ta],inc.

l.[bh]sp rt5,var,inc
     Load value of var into register rt5 and increment $ta by amount inc. la $ta,var and then l[bh]si.bi rt5,[$ta],inc

l.[bh]spc rt5,inc
     Continue loading value of var into register rt5 and increment $ta by amount inc. l[bh]si.bi rt5,[$ta],inc.

s.[bhw] rt5,var
     Store register rt5 to var. sethi $ta,hi20(var) and then s[bhw]i rt5,[$ta+lo12(var)]

s.[bhw]p rt5,var,inc
     Store register rt5 to var and increment $ta by amount inc. la $ta,var and then s[bhw]i.bi rt5,[$ta],inc

s.[bhw]pc rt5,inc
     Continue storing register rt5 to var and increment $ta by amount inc. s[bhw]i.bi rt5,[$ta],inc.

not rt5,ra5
     Alias of nor rt5,ra5,ra5.

neg rt5,ra5
     Alias of subri rt5,ra5,0.

br rb5
     Depending on how it is assembled, it is translated into r5 rb5 or jr rb5.

b label
     Branch to label depending on how it is assembled, it is translated into j8 label, j label, or "la $ta,label br $ta".

bral rb5
     Alias of jral br5 depending on how it is assembled, it is translated into jral5 rb5 or jral rb5.

bal fname
     Alias of jal fname depending on how it is assembled, it is translated into jal fname or "la $ta,fname bral $ta".

call fname
     Call function fname same as jal fname.

move rt5,ra5
     For 16-bit, this is mov55 rt5,ra5. For no 16-bit, this is ori rt5,ra5,0.

move rt5,var
     This is the same as l.w rt5,var.

move rt5,imm32
     This is the same as li rt5,imm32.

pushm ra5,rb5
     Push contents of registers from ra5 to rb5 into stack.

push ra5
     Push content of register ra5 into stack. (same pushm ra5,ra5).

push.d var
     Push value of double-word variable var into stack.

push.w var
     Push value of word variable var into stack.

push.h var
     Push value of half-word variable var into stack.

push.b var
     Push value of byte variable var into stack.

pusha var
     Push 32-bit address of variable var into stack.

pushi imm32
     Push 32-bit immediate value into stack.

popm ra5,rb5
     Pop top of stack values into registers ra5 to rb5.

pop rt5
     Pop top of stack value into register. (same as popm rt5,rt5.)

pop.d var,ra5
     Pop value of double-word variable var from stack using register ra5 as 2nd scratch register. (1st is $ta)

pop.w var,ra5
     Pop value of word variable var from stack using register ra5.

pop.h var,ra5
     Pop value of half-word variable var from stack using register ra5.

pop.b var,ra5
     Pop value of byte variable var from stack using register ra5.