/* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * GPL LICENSE SUMMARY * * Copyright(c) 2007,2008 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. * The full GNU General Public License is included in this distribution * in the file called LICENSE.GPL. * * Contact Information: * Intel Corporation * * BSD LICENSE * * Copyright(c) 2007,2008 Intel Corporation. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * Neither the name of Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * * version: Embedded.L.0.7.187 */ /* * NetApp change history @ 21-Dec-2011 (under CONFIG_NETAPP_HWDD): * - renamed driver locally to hwdd_gpio.c * - var "DRIVERNAME" changed to "hwdd_gpio", from "gpio_ref" * - LPC_DEVICE_ID changed to 0x2918(from 0x5031) w.r.t ICH9 spec for Carnegie, * -- This should be changed(value awaited) w.r.t PCH Spec accordingly for BBA * - Enhancement this driver needs, should the GPIO signals goes beyond 64 * (-- now itself count is 76 - referred recent PCM doc dated 20-Dec-2011) * -- Need to add offsets for SEL3 and LVL3 as per PCH doc: * --- Offset 40h: GPIO_USE_SEL3 * --- Offset 44h: GP_IO_SEL3 * --- Offset 48h: GP_LVL3 * --- Offset 60h: GP_RST_SEL * -- Max gpio signals from 64 to 128 and thereby increase memory size for same from 64B to 128B * -- LPC device spec(Bus/Dev/Fn.) on PCI bus w.r.t. PCH spec. (eg: LPC_DEVICE_ID) * -- any other change to incorporate above comments or other! */ /* NetApp change history @ 20-Jul-2012: * added support for another 32 pins for PCH, now total of 96 pins * LVL3, SEL3 added for PCH's pins beyond 64 * macro PCH and ICH9 introduced */ /***************************************************************************** * Module name: * gpio * * Abstract: * This header file is to be included by the gpio.c file only. * It is OS independent. * * Revision: * * *****************************************************************************/ #ifndef COMMON_H #define COMMON_H #define PCH 1 //#define ICH9 1 //offset into low pin count(LPC) config space of the GPIO base address #define GPIO_BAR_OFFSET 0x48 //vendor and device IDs of LPC device #define LPC_VENDOR_ID 0x8086 #ifdef CONFIG_NETAPP_HWDD #ifdef PCH #define LPC_DEVICE_ID 0x1D41 // PCH-0x1D41 #define SEL 3 #define LVL 3 #define MAX_GPIO_SIGNALS 96 #define GPIO_MEM_SIZE 96 //GPIO register memory size in bytes #endif #ifdef ICH9 #define LPC_DEVICE_ID 0x2918 // ICH9-0x2918 #define SEL 2 #define LVL 2 #define MAX_GPIO_SIGNALS 64 #define GPIO_MEM_SIZE 64 //GPIO register memory size in bytes #endif #else #define LPC_DEVICE_ID 0x5031 #define SEL 2 #define LVL 2 #define MAX_GPIO_SIGNALS 64 #define GPIO_MEM_SIZE 64 //GPIO register memory size in bytes #endif //Location of the LPC device on the PCI bus #define LPC_BUS_NUM 0 #define LPC_DEVICE_NUM 31 #define LPC_FUNCTION_NUM 0 //msb bit number of a GPIO register #define GPIO_REG_MSB 31 //number of bits in a GPIO register #define GPIO_REG_BITS 32 // offsets for gpio registers #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04 #define GP_LVL 0x0c #define GPO_BLINK 0x18 #define GPI_INV 0x2c #define GPIO_USE_SEL2 0x30 #define GP_IO_SEL2 0x34 #define GP_LVL2 0x38 #ifdef PCH #define GPIO_USE_SEL3 0x40 #define GP_IO_SEL3 0x44 #define GP_LVL3 0x48 #define GP_RST_SEL 0x60 #endif /****************************************************************************** Description: This structure contains an IO address to each of the gpio registers contained in the hardware device memory. Each register can then be accessed using the IO address. *****************************************************************************/ typedef struct gpio_regs_s { unsigned int gpio_use_sel; // alternative or gpio function (signals 0-31) unsigned int gp_io_sel; // input or output (signals 0-31) unsigned int gp_lvl; // low or high level (signals 0-31) unsigned int gpo_blink; // blink function (signals 0-31) unsigned int gpi_inv; // invert function (signals 0-31) unsigned int gpio_use_sel2; // alternative or gpio function (signals 32-63) unsigned int gp_io_sel2; // input or output (signals 32-63) unsigned int gp_lvl2; // low or high level (signals 32-63) #ifdef PCH unsigned int gpio_use_sel3; // alternative or gpio function (signals 64-95) unsigned int gp_io_sel3; // input or output (signals 64-95) unsigned int gp_lvl3; // low or high level (signals 64-95) #endif } gpio_regs_t; #endif