/*
 * $Id$
 * HWDD NVRAM  module: main header file 
 * Copyright (c) 2011 Network Appliance, Inc.
 *
 */
#ifndef HWDD_NVRAM_H
#define HWDD_NVRAM_H

#include <linux/hwdd_logger.h>

#define NVRAM_VERSION      "1.0"
#define NVRAM_DEV		"nvram"

/* NVRAM PCI IDs */
#define VENDOR_ID_NVRAM9        0x1275
#define DEVICE_ID_NVRAM9        0x000A

/* NVRAM MRI IDs */
#define MRI_NVRAM9_DEVID	0x4d01
#define MRI_NVRAM9_ELEID	0x0001
#define MRI_TWI_ELEID		0x0005

extern int dip_access(u8 dip_id);
extern int get_mri_base(u16 id, int instance);
extern void twi_init(void);
extern int read_reg(int offset, u32 *value);
extern int write_reg(int offset, u32 value);

/* Refer to NVRAM FPGA spec for detailed information about the below structures */

struct mri_devhdr {	/* This structure represents the MRI Base Element */
	u32 element; 	/* [31:16] Next ele, [15:0] Ele ID */
	u32 flist;
	u32 rev;	/* [31:24] Rev Major, [23:16] Rev Minor, [15:0] Rev Micro */
	u32 tstamp;
	u32 dev_ctrl;
	u32 intr_stat;
	u32 intr_mask;
};

/* 
 * Intention of this structure is to represent NVRAM9 element, 
 * it is incomplete as of now and is not used in the code. Will either
 * enhance it or delete this completely going ahead.
 */

struct mri_elehdr {	
	u32 element;
	u32 flist;
};

#endif /* HWDD_NVRAM_H */