/*******************************************************************************

HWDD memory module
Copyright (c) 2011 Network Appliance, Inc.

hwdd_support_fpga.h: main header file for HWDD support FPGA module
*******************************************************************************/

#ifndef _HWDD_SUPPORT_FPGA_H_
#define _HWDD_SUPPORT_FPGA_H_

#include <linux/hwdd_logger.h>


#define 		FPGA_CONSOLE_PORT_STATUS_REG	  		 0x0000
#define 		FPGA_DEBUG_PORT_CONTROL_REG  			 0x0004

#define 		FPGA_MIDPLN_CNTRL_N_STATUS_REG 		 0x1000
#define		FPGA_MIDPLN_LCL_BUS_REG					 0x1004
#define		FPGA_MIDPLN_TIMER_RESTART_REG			 0x1008
#define		FPGA_MIDPLN_RMT_BUS_REG					 0x100C
#define		FPGA_MIDPLN_LCL_ERR_REG					 0x1010
#define		FPGA_MIDPLN_RMT_ERR_REG			 	  	0x1014
#define		FPGA_MIDPLN_SHRT_TIMEOUT_REG		 	0x1020
#define		FPGA_MIDPLN_LONG_TIMEOUT_REG		 	0x1024

#define		FPGA_FIFO_CNTRL_REG					 0x2000
#define		FPGA_FIFO_TIME_STMP_REG				 0x2004
#define		FPGA_FIFO_ID_REG						 0x2008
#define		FPGA_FIFO_ENTRY_REG0					 0x2010
#define		FPGA_FIFO_ENTRY_REG1					 0x2014
#define		FPGA_FIFO_ENTRY_REG2					 0x2018

#define		FPGA_SIGNAL_STATUS_REG0				 0x2020
#define		FPGA_SIGNAL_STATUS_REG1				 0x2024
#define		FPGA_SIGNAL_STATUS_REG2				 0x2028
#define		FPGA_SIGNAL_ENABLE_REG0				 0x2030
#define		FPGA_SIGNAL_ENABLE_REG1				 0x2034
#define		FPGA_SIGNAL_ENABLE_REG2				 0x2038

#define 		FPGA_INTR_ENABLE_REG0				 0x3000
#define		FPGA_INTR_ENABLE_REG1				 0x3004
#define		FPGA_INTR_ENABLE_REG2				 0x3008
#define		FPGA_INTR_TYPE_REG0			     	0x3010
#define		FPGA_INTR_TYPE_REG1					 0x3014
#define		FPGA_INTR_TYPE_REG2				 0x3018
#define		FPGA_INTR_POLARITY_REG0			 0x3020
#define		FPGA_INTR_POLARITY_REG1			 0x3024
#define		FPGA_INTR_POLARITY_REG2			 0x3028
#define		FPGA_INTR_STATUS_REG0			 0x3030
#define		FPGA_INTR_STATUS_REG1			 0x3034
#define		FPGA_INTR_STATUS_REG2			 0x3038

#define		XDP_WTCHDOG_RESTART_REG		   0x4FFC

#define		DATA_BUS_TEST_REG					0x7FF8
#define		ADDR_BUS_TEST_REG				   0x7FFC
#define     CHKBRD_PTRN						   0x5A



#define 		FPGA_READ_REG(a, reg)	(\
			readl((a) + (reg)))	

#define 		FPGA_READ_REG16(a, reg)	(\
			readw((a) + (reg)))	

#define 		FPGA_READ_REG8(a, reg)	(\
			readb((a) + (reg)))	

#define 		FPGA_WRITE_REG(a, reg, value)	(\
			writel((value), (a) + (reg)))	

#define 		FPGA_WRITE_REG16(a, reg, value)	(\
			writew((value), (a) + (reg)))	

#define 		FPGA_WRITE_REG8(a, reg, value)	(\
			writeb((value), (a) + (reg)))	


#endif /* _HWDD_SUPPORT_FPGA_H_ */